/*
 * Copyright (c) 2024 Syntiant Corp.  All rights reserved.
 * Contact at http://www.syntiant.com
 *
 * This software is available to you under a choice of one of two licenses.
 * You may choose to be licensed under the terms of the GNU General Public
 * License (GPL) Version 2, available from the file LICENSE in the main
 * directory of this source tree, or the OpenIB.org BSD license below.  Any
 * code involving Linux software will require selection of the GNU General
 * Public License (GPL) Version 2.
 *
 * OPENIB.ORG BSD LICENSE
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 	** SDK: v112.3.5-Samsung **
*/

/*
 * ******* Automatically generated for ndp120 v2.00  DO NOT MODIFY!!!!!
 *          Generated Wed Sep 30 21:53:23 2020 UTC
 */
#ifndef NDP120_REGS_H
#define NDP120_REGS_H

/*
 * block ndp120.bootram, base 0x00000000
 */
#define NDP120_BOOTRAM 0x00000000U
#define NDP120_BOOTRAM_SIZE 0x00004000U

/*
 * block ndp120.bootrom, base 0x01000000
 */
#define NDP120_BOOTROM 0x01000000U
#define NDP120_BOOTROM_SIZE 0x00002000U

/*
 * block ndp120.bootram_remap, base 0x1fffc000
 */
#define NDP120_BOOTRAM_REMAP 0x1fffc000U
#define NDP120_BOOTRAM_REMAP_SIZE 0x00004000U

/*
 * block ndp120.ram, base 0x20000000
 */
#define NDP120_RAM 0x20000000U
#define NDP120_RAM_SIZE 0x00008000U

/*
 * block ndp120.dsp_iram, base 0x30000000
 */
#define NDP120_DSP_IRAM 0x30000000U
#define NDP120_DSP_IRAM_SIZE 0x00018000U

/*
 * block ndp120.dsp_dram, base 0x30080000
 */
#define NDP120_DSP_DRAM 0x30080000U
#define NDP120_DSP_DRAM_SIZE 0x00030000U

/*
 * block ndp120.dualtimer0, base 0x40002000
 */
#define NDP120_DUALTIMER0 0x40002000U
#define NDP120_DUALTIMER0_SIZE 0x00001000U

/*
 * block ndp120.uart0, base 0x40004000
 */
#define NDP120_UART0 0x40004000U
#define NDP120_UART0_SIZE 0x00001000U
/* register ndp120.uart0.data */
#define NDP120_UART0_DATA 0x40004000U
/* register ndp120.uart0.stat */
#define NDP120_UART0_STAT 0x40004004U
#define NDP120_UART0_STAT_TXBUF_FULL_SHIFT 0
#define NDP120_UART0_STAT_TXBUF_FULL_MASK 0x00000001U
#define NDP120_UART0_STAT_TXBUF_FULL(v) \
        ((v) << NDP120_UART0_STAT_TXBUF_FULL_SHIFT)
#define NDP120_UART0_STAT_TXBUF_FULL_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_STAT_TXBUF_FULL_SHIFT))
#define NDP120_UART0_STAT_TXBUF_FULL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_STAT_TXBUF_FULL_MASK) | ((v) << NDP120_UART0_STAT_TXBUF_FULL_SHIFT))
#define NDP120_UART0_STAT_TXBUF_FULL_EXTRACT(x) \
        (((x) & NDP120_UART0_STAT_TXBUF_FULL_MASK) >> NDP120_UART0_STAT_TXBUF_FULL_SHIFT)
#define NDP120_UART0_STAT_RXBUF_FULL_SHIFT 1
#define NDP120_UART0_STAT_RXBUF_FULL_MASK 0x00000002U
#define NDP120_UART0_STAT_RXBUF_FULL(v) \
        ((v) << NDP120_UART0_STAT_RXBUF_FULL_SHIFT)
#define NDP120_UART0_STAT_RXBUF_FULL_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_STAT_RXBUF_FULL_SHIFT))
#define NDP120_UART0_STAT_RXBUF_FULL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_STAT_RXBUF_FULL_MASK) | ((v) << NDP120_UART0_STAT_RXBUF_FULL_SHIFT))
#define NDP120_UART0_STAT_RXBUF_FULL_EXTRACT(x) \
        (((x) & NDP120_UART0_STAT_RXBUF_FULL_MASK) >> NDP120_UART0_STAT_RXBUF_FULL_SHIFT)
#define NDP120_UART0_STAT_TXBUF_OVERRUN_SHIFT 2
#define NDP120_UART0_STAT_TXBUF_OVERRUN_MASK 0x00000004U
#define NDP120_UART0_STAT_TXBUF_OVERRUN(v) \
        ((v) << NDP120_UART0_STAT_TXBUF_OVERRUN_SHIFT)
#define NDP120_UART0_STAT_TXBUF_OVERRUN_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_STAT_TXBUF_OVERRUN_SHIFT))
#define NDP120_UART0_STAT_TXBUF_OVERRUN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_STAT_TXBUF_OVERRUN_MASK) | ((v) << NDP120_UART0_STAT_TXBUF_OVERRUN_SHIFT))
#define NDP120_UART0_STAT_TXBUF_OVERRUN_EXTRACT(x) \
        (((x) & NDP120_UART0_STAT_TXBUF_OVERRUN_MASK) >> NDP120_UART0_STAT_TXBUF_OVERRUN_SHIFT)
#define NDP120_UART0_STAT_RXBUF_OVERRUN_SHIFT 3
#define NDP120_UART0_STAT_RXBUF_OVERRUN_MASK 0x00000008U
#define NDP120_UART0_STAT_RXBUF_OVERRUN(v) \
        ((v) << NDP120_UART0_STAT_RXBUF_OVERRUN_SHIFT)
#define NDP120_UART0_STAT_RXBUF_OVERRUN_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_STAT_RXBUF_OVERRUN_SHIFT))
#define NDP120_UART0_STAT_RXBUF_OVERRUN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_STAT_RXBUF_OVERRUN_MASK) | ((v) << NDP120_UART0_STAT_RXBUF_OVERRUN_SHIFT))
#define NDP120_UART0_STAT_RXBUF_OVERRUN_EXTRACT(x) \
        (((x) & NDP120_UART0_STAT_RXBUF_OVERRUN_MASK) >> NDP120_UART0_STAT_RXBUF_OVERRUN_SHIFT)
/* register ndp120.uart0.ctrl */
#define NDP120_UART0_CTRL 0x40004008U
#define NDP120_UART0_CTRL_TX_ENABLE_SHIFT 0
#define NDP120_UART0_CTRL_TX_ENABLE_MASK 0x00000001U
#define NDP120_UART0_CTRL_TX_ENABLE(v) \
        ((v) << NDP120_UART0_CTRL_TX_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_TX_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_CTRL_TX_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_TX_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_CTRL_TX_ENABLE_MASK) | ((v) << NDP120_UART0_CTRL_TX_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_TX_ENABLE_EXTRACT(x) \
        (((x) & NDP120_UART0_CTRL_TX_ENABLE_MASK) >> NDP120_UART0_CTRL_TX_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_TX_ENABLE_DEFAULT 0x00000000U
#define NDP120_UART0_CTRL_RX_ENABLE_SHIFT 1
#define NDP120_UART0_CTRL_RX_ENABLE_MASK 0x00000002U
#define NDP120_UART0_CTRL_RX_ENABLE(v) \
        ((v) << NDP120_UART0_CTRL_RX_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_RX_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_CTRL_RX_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_RX_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_CTRL_RX_ENABLE_MASK) | ((v) << NDP120_UART0_CTRL_RX_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_RX_ENABLE_EXTRACT(x) \
        (((x) & NDP120_UART0_CTRL_RX_ENABLE_MASK) >> NDP120_UART0_CTRL_RX_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_RX_ENABLE_DEFAULT 0x00000000U
#define NDP120_UART0_CTRL_TX_INT_ENABLE_SHIFT 2
#define NDP120_UART0_CTRL_TX_INT_ENABLE_MASK 0x00000004U
#define NDP120_UART0_CTRL_TX_INT_ENABLE(v) \
        ((v) << NDP120_UART0_CTRL_TX_INT_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_TX_INT_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_CTRL_TX_INT_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_TX_INT_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_CTRL_TX_INT_ENABLE_MASK) | ((v) << NDP120_UART0_CTRL_TX_INT_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_TX_INT_ENABLE_EXTRACT(x) \
        (((x) & NDP120_UART0_CTRL_TX_INT_ENABLE_MASK) >> NDP120_UART0_CTRL_TX_INT_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_TX_INT_ENABLE_DEFAULT 0x00000000U
#define NDP120_UART0_CTRL_RX_INT_ENABLE_SHIFT 3
#define NDP120_UART0_CTRL_RX_INT_ENABLE_MASK 0x00000008U
#define NDP120_UART0_CTRL_RX_INT_ENABLE(v) \
        ((v) << NDP120_UART0_CTRL_RX_INT_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_RX_INT_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_CTRL_RX_INT_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_RX_INT_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_CTRL_RX_INT_ENABLE_MASK) | ((v) << NDP120_UART0_CTRL_RX_INT_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_RX_INT_ENABLE_EXTRACT(x) \
        (((x) & NDP120_UART0_CTRL_RX_INT_ENABLE_MASK) >> NDP120_UART0_CTRL_RX_INT_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_RX_INT_ENABLE_DEFAULT 0x00000000U
#define NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_SHIFT 4
#define NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_MASK 0x00000010U
#define NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE(v) \
        ((v) << NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_MASK) | ((v) << NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_EXTRACT(x) \
        (((x) & NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_MASK) >> NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_TX_OVERRUN_INT_ENABLE_DEFAULT 0x00000000U
#define NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_SHIFT 5
#define NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_MASK 0x00000020U
#define NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE(v) \
        ((v) << NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_MASK) | ((v) << NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_SHIFT))
#define NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_EXTRACT(x) \
        (((x) & NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_MASK) >> NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_SHIFT)
#define NDP120_UART0_CTRL_RX_OVERRUN_INT_ENABLE_DEFAULT 0x00000000U
#define NDP120_UART0_CTRL_TEST_MODE_SHIFT 6
#define NDP120_UART0_CTRL_TEST_MODE_MASK 0x00000040U
#define NDP120_UART0_CTRL_TEST_MODE(v) \
        ((v) << NDP120_UART0_CTRL_TEST_MODE_SHIFT)
#define NDP120_UART0_CTRL_TEST_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_CTRL_TEST_MODE_SHIFT))
#define NDP120_UART0_CTRL_TEST_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_CTRL_TEST_MODE_MASK) | ((v) << NDP120_UART0_CTRL_TEST_MODE_SHIFT))
#define NDP120_UART0_CTRL_TEST_MODE_EXTRACT(x) \
        (((x) & NDP120_UART0_CTRL_TEST_MODE_MASK) >> NDP120_UART0_CTRL_TEST_MODE_SHIFT)
#define NDP120_UART0_CTRL_TEST_MODE_DEFAULT 0x00000000U
#define NDP120_UART0_CTRL_DEFAULT 0x00000000U 
/* register ndp120.uart0.intr_status */
#define NDP120_UART0_INTR_STATUS 0x4000400cU
#define NDP120_UART0_INTR_STATUS_TX_INT_SHIFT 0
#define NDP120_UART0_INTR_STATUS_TX_INT_MASK 0x00000001U
#define NDP120_UART0_INTR_STATUS_TX_INT(v) \
        ((v) << NDP120_UART0_INTR_STATUS_TX_INT_SHIFT)
#define NDP120_UART0_INTR_STATUS_TX_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_INTR_STATUS_TX_INT_SHIFT))
#define NDP120_UART0_INTR_STATUS_TX_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_INTR_STATUS_TX_INT_MASK) | ((v) << NDP120_UART0_INTR_STATUS_TX_INT_SHIFT))
#define NDP120_UART0_INTR_STATUS_TX_INT_EXTRACT(x) \
        (((x) & NDP120_UART0_INTR_STATUS_TX_INT_MASK) >> NDP120_UART0_INTR_STATUS_TX_INT_SHIFT)
#define NDP120_UART0_INTR_STATUS_RX_INT_SHIFT 1
#define NDP120_UART0_INTR_STATUS_RX_INT_MASK 0x00000002U
#define NDP120_UART0_INTR_STATUS_RX_INT(v) \
        ((v) << NDP120_UART0_INTR_STATUS_RX_INT_SHIFT)
#define NDP120_UART0_INTR_STATUS_RX_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_INTR_STATUS_RX_INT_SHIFT))
#define NDP120_UART0_INTR_STATUS_RX_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_INTR_STATUS_RX_INT_MASK) | ((v) << NDP120_UART0_INTR_STATUS_RX_INT_SHIFT))
#define NDP120_UART0_INTR_STATUS_RX_INT_EXTRACT(x) \
        (((x) & NDP120_UART0_INTR_STATUS_RX_INT_MASK) >> NDP120_UART0_INTR_STATUS_RX_INT_SHIFT)
#define NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT_SHIFT 2
#define NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT_MASK 0x00000004U
#define NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT(v) \
        ((v) << NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT_SHIFT)
#define NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT_SHIFT))
#define NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT_MASK) | ((v) << NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT_SHIFT))
#define NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT_EXTRACT(x) \
        (((x) & NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT_MASK) >> NDP120_UART0_INTR_STATUS_TX_OVERRUN_INT_SHIFT)
#define NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT_SHIFT 3
#define NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT_MASK 0x00000008U
#define NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT(v) \
        ((v) << NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT_SHIFT)
#define NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT_SHIFT))
#define NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT_MASK) | ((v) << NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT_SHIFT))
#define NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT_EXTRACT(x) \
        (((x) & NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT_MASK) >> NDP120_UART0_INTR_STATUS_RX_OVERRUN_INT_SHIFT)
/* register ndp120.uart0.bauddiv */
#define NDP120_UART0_BAUDDIV 0x40004010U
#define NDP120_UART0_BAUDDIV_DIVIDER_SHIFT 0
#define NDP120_UART0_BAUDDIV_DIVIDER_MASK 0x0007ffffU
#define NDP120_UART0_BAUDDIV_DIVIDER(v) \
        ((v) << NDP120_UART0_BAUDDIV_DIVIDER_SHIFT)
#define NDP120_UART0_BAUDDIV_DIVIDER_INSERT(x, v) \
        ((x) | ((v) << NDP120_UART0_BAUDDIV_DIVIDER_SHIFT))
#define NDP120_UART0_BAUDDIV_DIVIDER_MASK_INSERT(x, v) \
        (((x) & ~NDP120_UART0_BAUDDIV_DIVIDER_MASK) | ((v) << NDP120_UART0_BAUDDIV_DIVIDER_SHIFT))
#define NDP120_UART0_BAUDDIV_DIVIDER_EXTRACT(x) \
        (((x) & NDP120_UART0_BAUDDIV_DIVIDER_MASK) >> NDP120_UART0_BAUDDIV_DIVIDER_SHIFT)
#define NDP120_UART0_BAUDDIV_DIVIDER_DEFAULT 0x00000010U
#define NDP120_UART0_BAUDDIV_DEFAULT 0x00000010U 

/*
 * block ndp120.chip_config, base 0x40009000
 */
#define NDP120_CHIP_CONFIG 0x40009000U
#define NDP120_CHIP_CONFIG_SIZE 0x00001000U
/* register ndp120.chip_config.id */
#define NDP120_CHIP_CONFIG_ID 0x40009000U
/* register ndp120.chip_config.clkctl0 */
#define NDP120_CHIP_CONFIG_CLKCTL0 0x40009004U
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_SHIFT 0
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_MASK 0x000003ffU
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_MASK) >> NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_SHIFT 10
#define NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_MASK 0x00000400U
#define NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_MASK) >> NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_MCURSTB_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_SHIFT 11
#define NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_MASK 0x00000800U
#define NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_MASK) >> NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_OTPRSTB_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_SHIFT 12
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_MASK 0x00001000U
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_MASK) >> NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_DNN_CLK_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_SHIFT 13
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_MASK 0x0000e000U
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_MASK) >> NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AUD_CLK_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_SHIFT 16
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_MASK 0x00010000U
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_MASK) >> NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_AESOTP_CLK_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_SHIFT 17
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_MASK 0x00020000U
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_MASK) >> NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_FORCE_PCLK_CLK_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_SHIFT 18
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_MASK 0x00040000U
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_MASK) >> NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUDBGEN_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_SHIFT 19
#define NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_MASK 0x00080000U
#define NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_MASK) >> NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_PLLRSTB_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_SHIFT 20
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_MASK 0x00300000U
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_MASK) >> NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_MCUCLKDIV_FROM_DSP_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_SHIFT 22
#define NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_MASK 0x00400000U
#define NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_MASK) >> NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL0_ENABLE_HCLK_EXTEND_ON_BOOTDISABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL0_DEFAULT 0x00080c01U 
/* register ndp120.chip_config.clkctl1 */
#define NDP120_CHIP_CONFIG_CLKCTL1 0x40009008U
#define NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_SHIFT 0
#define NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_CLKCTL1_REFSEL(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_MASK) >> NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_CLKIN 0x0U
#define NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_XTALIN 0x1U
#define NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_MAX 0x1U
#define NDP120_CHIP_CONFIG_CLKCTL1_REFSEL_VALID(v) \
        (v >= 0 && v <= 1)
#define NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_SHIFT 1
#define NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_MASK) >> NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_FLL 0x0U
#define NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_PLL 0x1U
#define NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_MAX 0x1U
#define NDP120_CHIP_CONFIG_CLKCTL1_CLKSEL_VALID(v) \
        (v >= 0 && v <= 1)
#define NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_SHIFT 2
#define NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_MASK) >> NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_INT 0x0U
#define NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_EXT 0x1U
#define NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_MAX 0x1U
#define NDP120_CHIP_CONFIG_CLKCTL1_EXTSEL_VALID(v) \
        (v >= 0 && v <= 1)
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_SHIFT 3
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_MASK) >> NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_IE_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_SHIFT 4
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_MASK 0x00000010U
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_MASK) >> NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_CLK_SMT_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_SHIFT 5
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_MASK 0x000000e0U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_MASK) >> NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_DISABLE 0x0U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_XTAL 0x1U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_EXT 0x2U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_PLL 0x3U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_OSC 0x4U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_MCU 0x5U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_AUD0 0x6U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_AUD1 0x7U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_MAX 0x7U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_SEL_VALID(v) \
        (v >= 0 && v <= 7)
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_SHIFT 8
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_MASK 0x00000100U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_MASK) >> NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_SHIFT 9
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_MASK 0x0007fe00U
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_MASK) >> NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL1_TESTCLK_DIVIDER_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_CLKCTL1_DEFAULT 0x00000218U 
/* register ndp120.chip_config.clkctl2 */
#define NDP120_CHIP_CONFIG_CLKCTL2 0x4000900cU
#define NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_SHIFT 0
#define NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_MASK) >> NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL2_UARTCLKENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_SHIFT 1
#define NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_MASK 0x0000001eU
#define NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_MASK) >> NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL2_RX_UART_SEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_SHIFT 5
#define NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_MASK 0x00000020U
#define NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_MASK) >> NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL2_TIMERCLKENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_SHIFT 6
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_MASK 0x00000040U
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_MASK) >> NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OSC_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_SHIFT 7
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_MASK 0x00000080U
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT(v) \
        ((v) << NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_MASK) | ((v) << NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_SHIFT))
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_MASK) >> NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_SHIFT)
#define NDP120_CHIP_CONFIG_CLKCTL2_XTAL_OUT_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CLKCTL2_DEFAULT 0x00000000U 
/* register array ndp120.chip_config.audctrl[2] */
#define NDP120_CHIP_CONFIG_AUDCTRL(i) (0x40009010U + ((i) << 2))
#define NDP120_CHIP_CONFIG_AUDCTRL_COUNT 2
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_SHIFT 0
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_MASK 0x000003ffU
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTDIV_DEFAULT 0x0000000aU
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_SHIFT 10
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_MASK 0x00000400U
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PDMCLKOUTNEEDED_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_SHIFT 11
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_MASK 0x00000800U
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_EN_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_SHIFT 12
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_MASK 0x00001000U
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_EN_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_SHIFT 13
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_MASK 0x00002000U
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK0_DRIVEHI_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_SHIFT 14
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_MASK 0x00004000U
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_PCLK1_DRIVEHI_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL_OE_SHIFT 15
#define NDP120_CHIP_CONFIG_AUDCTRL_OE_MASK 0x00018000U
#define NDP120_CHIP_CONFIG_AUDCTRL_OE(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL_OE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_OE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_OE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_OE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL_OE_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_OE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_OE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL_OE_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL_OE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_OE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL_IE_SHIFT 17
#define NDP120_CHIP_CONFIG_AUDCTRL_IE_MASK 0x000e0000U
#define NDP120_CHIP_CONFIG_AUDCTRL_IE(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL_IE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_IE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_IE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_IE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL_IE_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_IE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_IE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL_IE_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL_IE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_IE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_SHIFT 20
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_MASK 0x00700000U
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL_MODE_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL_MODE_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_DISABLE 0x0U
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_PDM_IN 0x1U
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_PDM_OUT 0x2U
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_PDM_THRU 0x3U
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_I2S_SLAVE 0x4U
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_I2S_MASTER 0x5U
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_MAX 0x5U
#define NDP120_CHIP_CONFIG_AUDCTRL_MODE_VALID(v) \
        (v >= 0 && v <= 5)
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_SHIFT 23
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_MASK 0x03800000U
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_DEFAULT 0x00000004U
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_TDM3 0x2U
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_TDM4 0x3U
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_TDM8 0x7U
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_MAX 0x7U
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_VALID(v) \
        (v == NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_TDM3 || v == NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_TDM4 || v == NDP120_CHIP_CONFIG_AUDCTRL_TDM_SIZE_TDM8)
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_SHIFT(i) (((i) * 3) + 26)
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_MASK(i) \
        (0x7U << NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_SHIFT(i))
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX(i, v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_SHIFT(i))
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_INSERT(x, i, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_SHIFT(i)))
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_MASK_INSERT(x, i, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_MASK(i)) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_SHIFT(i)))
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_EXTRACT(x, i) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_MASK(i)) >> NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_SHIFT(i))
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_COUNT 2
#define NDP120_CHIP_CONFIG_AUDCTRL_TDM_INDEX_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL_DEFAULT 0x0200000aU 
/* register ndp120.chip_config.audctrl2 */
#define NDP120_CHIP_CONFIG_AUDCTRL2 0x40009018U
#define NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_SHIFT 0
#define NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_AUDCTRL2_RSTB(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_RSTB_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_SHIFT 1
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_MASK 0x000007feU
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTDIV_DEFAULT 0x00000002U
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_SHIFT 11
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_MASK 0x00000800U
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKOUTNEEDED_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_SHIFT 12
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_MASK 0x003ff000U
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_AUD2CLKDIV_DEFAULT 0x00000004U
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE_SHIFT 22
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE_MASK 0x01c00000U
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_OE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_OE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL2_OE_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_OE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL2_OE_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL2_OE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE_DISABLE 0x0U
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE_I2S_SLAVE 0x4U
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE_I2S_MASTER 0x7U
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE_MAX 0x7U
#define NDP120_CHIP_CONFIG_AUDCTRL2_OE_VALID(v) \
        (v == NDP120_CHIP_CONFIG_AUDCTRL2_OE_DISABLE || v == NDP120_CHIP_CONFIG_AUDCTRL2_OE_I2S_SLAVE || v == NDP120_CHIP_CONFIG_AUDCTRL2_OE_I2S_MASTER)
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE_SHIFT 25
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE_MASK 0x06000000U
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE(v) \
        ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_IE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_IE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AUDCTRL2_IE_MASK) | ((v) << NDP120_CHIP_CONFIG_AUDCTRL2_IE_SHIFT))
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AUDCTRL2_IE_MASK) >> NDP120_CHIP_CONFIG_AUDCTRL2_IE_SHIFT)
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE_DISABLE 0x0U
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE_I2S_MASTER 0x2U
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE_I2S_SLAVE 0x3U
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE_MAX 0x3U
#define NDP120_CHIP_CONFIG_AUDCTRL2_IE_VALID(v) \
        (v == NDP120_CHIP_CONFIG_AUDCTRL2_IE_DISABLE || v == NDP120_CHIP_CONFIG_AUDCTRL2_IE_I2S_MASTER || v == NDP120_CHIP_CONFIG_AUDCTRL2_IE_I2S_SLAVE)
#define NDP120_CHIP_CONFIG_AUDCTRL2_DEFAULT 0x00004005U 
/* register ndp120.chip_config.gpiosel */
#define NDP120_CHIP_CONFIG_GPIOSEL 0x4000901cU
#define NDP120_CHIP_CONFIG_GPIOSEL_SEL_SHIFT 0
#define NDP120_CHIP_CONFIG_GPIOSEL_SEL_MASK 0x07ffffffU
#define NDP120_CHIP_CONFIG_GPIOSEL_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_GPIOSEL_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOSEL_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_GPIOSEL_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOSEL_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_GPIOSEL_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_GPIOSEL_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOSEL_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_GPIOSEL_SEL_MASK) >> NDP120_CHIP_CONFIG_GPIOSEL_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOSEL_SEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_GPIOSEL_DEFAULT 0x00000000U 
/* register ndp120.chip_config.gpiood */
#define NDP120_CHIP_CONFIG_GPIOOD 0x40009020U
#define NDP120_CHIP_CONFIG_GPIOOD_OD_SHIFT 0
#define NDP120_CHIP_CONFIG_GPIOOD_OD_MASK 0x07ffffffU
#define NDP120_CHIP_CONFIG_GPIOOD_OD(v) \
        ((v) << NDP120_CHIP_CONFIG_GPIOOD_OD_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOOD_OD_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_GPIOOD_OD_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOOD_OD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_GPIOOD_OD_MASK) | ((v) << NDP120_CHIP_CONFIG_GPIOOD_OD_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOOD_OD_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_GPIOOD_OD_MASK) >> NDP120_CHIP_CONFIG_GPIOOD_OD_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOOD_OD_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_GPIOOD_DEFAULT 0x00000000U 
/* register ndp120.chip_config.gpioie */
#define NDP120_CHIP_CONFIG_GPIOIE 0x40009024U
#define NDP120_CHIP_CONFIG_GPIOIE_IE_SHIFT 0
#define NDP120_CHIP_CONFIG_GPIOIE_IE_MASK 0x07ffffffU
#define NDP120_CHIP_CONFIG_GPIOIE_IE(v) \
        ((v) << NDP120_CHIP_CONFIG_GPIOIE_IE_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOIE_IE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_GPIOIE_IE_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOIE_IE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_GPIOIE_IE_MASK) | ((v) << NDP120_CHIP_CONFIG_GPIOIE_IE_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOIE_IE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_GPIOIE_IE_MASK) >> NDP120_CHIP_CONFIG_GPIOIE_IE_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOIE_IE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_GPIOIE_DEFAULT 0x00000000U 
/* register ndp120.chip_config.gpiopu */
#define NDP120_CHIP_CONFIG_GPIOPU 0x40009028U
#define NDP120_CHIP_CONFIG_GPIOPU_PU_SHIFT 0
#define NDP120_CHIP_CONFIG_GPIOPU_PU_MASK 0x07ffffffU
#define NDP120_CHIP_CONFIG_GPIOPU_PU(v) \
        ((v) << NDP120_CHIP_CONFIG_GPIOPU_PU_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOPU_PU_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_GPIOPU_PU_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOPU_PU_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_GPIOPU_PU_MASK) | ((v) << NDP120_CHIP_CONFIG_GPIOPU_PU_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOPU_PU_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_GPIOPU_PU_MASK) >> NDP120_CHIP_CONFIG_GPIOPU_PU_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOPU_PU_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_SHIFT 27
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_MASK 0x38000000U
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU(v) \
        ((v) << NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_MASK) | ((v) << NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_MASK) >> NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_DISABLE 0x0U
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_SSB 0x1U
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_ALL 0x7U
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_MAX 0x7U
#define NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_VALID(v) \
        (v == NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_DISABLE || v == NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_SSB || v == NDP120_CHIP_CONFIG_GPIOPU_SPI_PU_ALL)
#define NDP120_CHIP_CONFIG_GPIOPU_DEFAULT 0x00000000U 
/* register ndp120.chip_config.gpiopd */
#define NDP120_CHIP_CONFIG_GPIOPD 0x4000902cU
#define NDP120_CHIP_CONFIG_GPIOPD_PD_SHIFT 0
#define NDP120_CHIP_CONFIG_GPIOPD_PD_MASK 0x07ffffffU
#define NDP120_CHIP_CONFIG_GPIOPD_PD(v) \
        ((v) << NDP120_CHIP_CONFIG_GPIOPD_PD_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOPD_PD_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_GPIOPD_PD_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOPD_PD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_GPIOPD_PD_MASK) | ((v) << NDP120_CHIP_CONFIG_GPIOPD_PD_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOPD_PD_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_GPIOPD_PD_MASK) >> NDP120_CHIP_CONFIG_GPIOPD_PD_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOPD_PD_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_SHIFT 27
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_MASK 0x38000000U
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD(v) \
        ((v) << NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_MASK) | ((v) << NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_MASK) >> NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_DISABLE 0x0U
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_SSB 0x1U
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_ALL 0x7U
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_MAX 0x7U
#define NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_VALID(v) \
        (v == NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_DISABLE || v == NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_SSB || v == NDP120_CHIP_CONFIG_GPIOPD_SPI_PD_ALL)
#define NDP120_CHIP_CONFIG_GPIOPD_DEFAULT 0x00000000U 
/* register ndp120.chip_config.gpiodrivelo */
#define NDP120_CHIP_CONFIG_GPIODRIVELO 0x40009030U
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_SHIFT(i) (((i) * 2) + 0)
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_MASK(i) \
        (0x3U << NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_SHIFT(i))
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE(i, v) \
        ((v) << NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_SHIFT(i))
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_INSERT(x, i, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_SHIFT(i)))
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_MASK_INSERT(x, i, v) \
        (((x) & ~NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_MASK(i)) | ((v) << NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_SHIFT(i)))
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_EXTRACT(x, i) \
        (((x) & NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_MASK(i)) >> NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_SHIFT(i))
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_COUNT 16
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_DRIVE2MA 0x0U
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_DRIVE4MA 0x1U
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_DRIVE6MA 0x2U
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_DRIVE8MA 0x3U
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_MAX 0x3U
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DRIVE_VALID(v) \
        (v >= 0 && v <= 3)
#define NDP120_CHIP_CONFIG_GPIODRIVELO_DEFAULT 0x00000000U 
/* register ndp120.chip_config.gpiodrivehi */
#define NDP120_CHIP_CONFIG_GPIODRIVEHI 0x40009034U
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_SHIFT(i) (((i) * 2) + 0)
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_MASK(i) \
        (0x3U << NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_SHIFT(i))
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE(i, v) \
        ((v) << NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_SHIFT(i))
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_INSERT(x, i, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_SHIFT(i)))
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_MASK_INSERT(x, i, v) \
        (((x) & ~NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_MASK(i)) | ((v) << NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_SHIFT(i)))
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_EXTRACT(x, i) \
        (((x) & NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_MASK(i)) >> NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_SHIFT(i))
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_COUNT 11
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_DRIVE2MA 0x0U
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_DRIVE4MA 0x1U
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_DRIVE6MA 0x2U
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_DRIVE8MA 0x3U
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_MAX 0x3U
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DRIVE_VALID(v) \
        (v >= 0 && v <= 3)
#define NDP120_CHIP_CONFIG_GPIODRIVEHI_DEFAULT 0x00000000U 
/* register ndp120.chip_config.gpioiddq */
#define NDP120_CHIP_CONFIG_GPIOIDDQ 0x40009038U
#define NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_SHIFT 0
#define NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_MASK 0x07ffffffU
#define NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ(v) \
        ((v) << NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_MASK) | ((v) << NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_SHIFT))
#define NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_MASK) >> NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_SHIFT)
#define NDP120_CHIP_CONFIG_GPIOIDDQ_IDDQ_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_GPIOIDDQ_DEFAULT 0x00000000U 
/* register ndp120.chip_config.spictl */
#define NDP120_CHIP_CONFIG_SPICTL 0x4000903cU
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_SHIFT 0
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_MASK 0x00000003U
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE(v) \
        ((v) << NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_MASK) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_MASK) >> NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_DISABLE 0x0U
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_FOUR_WIRE 0x1U
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_THREE_WIRE 0x2U
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_QUAD 0x3U
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_MAX 0x3U
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_MODE_VALID(v) \
        (v >= 0 && v <= 3)
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_SHIFT 2
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_READ(v) \
        ((v) << NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_MASK) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_MASK) >> NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_READ_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_SHIFT 3
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_MASK 0x00001ff8U
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV(v) \
        ((v) << NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_MASK) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_MASK) >> NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MSPI_CLKDIV_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_SPICTL_MODE_SHIFT 13
#define NDP120_CHIP_CONFIG_SPICTL_MODE_MASK 0x00006000U
#define NDP120_CHIP_CONFIG_SPICTL_MODE(v) \
        ((v) << NDP120_CHIP_CONFIG_SPICTL_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPICTL_MODE_MASK) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPICTL_MODE_MASK) >> NDP120_CHIP_CONFIG_SPICTL_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MODE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPICTL_MODE_STANDBY 0x0U
#define NDP120_CHIP_CONFIG_SPICTL_MODE_SS 0x1U
#define NDP120_CHIP_CONFIG_SPICTL_MODE_TRANSFER 0x2U
#define NDP120_CHIP_CONFIG_SPICTL_MODE_UPDATE 0x3U
#define NDP120_CHIP_CONFIG_SPICTL_MODE_MAX 0x3U
#define NDP120_CHIP_CONFIG_SPICTL_MODE_VALID(v) \
        (v >= 0 && v <= 3)
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_SHIFT 15
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_MASK 0x00078000U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES(v) \
        ((v) << NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_MASK) | ((v) << NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_MASK) >> NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_ONE_BYTE 0x0U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_TWO_BYTE 0x1U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_THREE_BYTE 0x2U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_FOUR_BYTE 0x3U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_FIVE_BYTE 0x4U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_SIX_BYTE 0x5U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_SEVEN_BYTE 0x6U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_EIGHT_BYTE 0x7U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_NINE_BYTE 0x8U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_TEN_BYTE 0x9U
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_ELEVEN_BYTE 0xaU
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_TWELVE_BYTE 0xbU
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_THIRTEEN_BYTE 0xcU
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_FOURTEEN_BYTE 0xdU
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_FIFTEEN_BYTE 0xeU
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_SIXTEEN_BYTE 0xfU
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_MAX 0xfU
#define NDP120_CHIP_CONFIG_SPICTL_NUMBYTES_VALID(v) \
        (v >= 0 && v <= 15)
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_SHIFT 19
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_MASK 0x00380000U
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_OE(v) \
        ((v) << NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_MASK) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_MASK) >> NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_OE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_SHIFT 22
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_MASK 0x00c00000U
#define NDP120_CHIP_CONFIG_SPICTL_MSSB(v) \
        ((v) << NDP120_CHIP_CONFIG_SPICTL_MSSB_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MSSB_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPICTL_MSSB_MASK) | ((v) << NDP120_CHIP_CONFIG_SPICTL_MSSB_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPICTL_MSSB_MASK) >> NDP120_CHIP_CONFIG_SPICTL_MSSB_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_MSSB0 0x0U
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_MMSB1 0x1U
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_MMSB2 0x2U
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_MAX 0x2U
#define NDP120_CHIP_CONFIG_SPICTL_MSSB_VALID(v) \
        (v >= 0 && v <= 2)
#define NDP120_CHIP_CONFIG_SPICTL_TYPE_SHIFT 24
#define NDP120_CHIP_CONFIG_SPICTL_TYPE_MASK 0x03000000U
#define NDP120_CHIP_CONFIG_SPICTL_TYPE(v) \
        ((v) << NDP120_CHIP_CONFIG_SPICTL_TYPE_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_TYPE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPICTL_TYPE_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_TYPE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPICTL_TYPE_MASK) | ((v) << NDP120_CHIP_CONFIG_SPICTL_TYPE_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_TYPE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPICTL_TYPE_MASK) >> NDP120_CHIP_CONFIG_SPICTL_TYPE_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_TYPE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPICTL_DONE_SHIFT 26
#define NDP120_CHIP_CONFIG_SPICTL_DONE_MASK 0x04000000U
#define NDP120_CHIP_CONFIG_SPICTL_DONE(v) \
        ((v) << NDP120_CHIP_CONFIG_SPICTL_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_DONE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPICTL_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_DONE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPICTL_DONE_MASK) | ((v) << NDP120_CHIP_CONFIG_SPICTL_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_DONE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPICTL_DONE_MASK) >> NDP120_CHIP_CONFIG_SPICTL_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_RSTB_SHIFT 27
#define NDP120_CHIP_CONFIG_SPICTL_RSTB_MASK 0x08000000U
#define NDP120_CHIP_CONFIG_SPICTL_RSTB(v) \
        ((v) << NDP120_CHIP_CONFIG_SPICTL_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_RSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPICTL_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_RSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPICTL_RSTB_MASK) | ((v) << NDP120_CHIP_CONFIG_SPICTL_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_RSTB_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPICTL_RSTB_MASK) >> NDP120_CHIP_CONFIG_SPICTL_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_RSTB_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_SHIFT 28
#define NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_MASK 0x10000000U
#define NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK(v) \
        ((v) << NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_MASK) | ((v) << NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_MASK) >> NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_SPICTL_FORCE_MSPI_CLK_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPICTL_DEFAULT 0x08000008U 
/* register array ndp120.chip_config.spitx[4] */
#define NDP120_CHIP_CONFIG_SPITX(i) (0x40009040U + ((i) << 2))
#define NDP120_CHIP_CONFIG_SPITX_COUNT 4
#define NDP120_CHIP_CONFIG_SPITX_TXBYTES_SHIFT 0
#define NDP120_CHIP_CONFIG_SPITX_TXBYTES_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_SPITX_TXBYTES(v) \
        ((v) << NDP120_CHIP_CONFIG_SPITX_TXBYTES_SHIFT)
#define NDP120_CHIP_CONFIG_SPITX_TXBYTES_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPITX_TXBYTES_SHIFT))
#define NDP120_CHIP_CONFIG_SPITX_TXBYTES_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPITX_TXBYTES_MASK) | ((v) << NDP120_CHIP_CONFIG_SPITX_TXBYTES_SHIFT))
#define NDP120_CHIP_CONFIG_SPITX_TXBYTES_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPITX_TXBYTES_MASK) >> NDP120_CHIP_CONFIG_SPITX_TXBYTES_SHIFT)
#define NDP120_CHIP_CONFIG_SPITX_TXBYTES_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPITX_DEFAULT 0x00000000U 
/* register array ndp120.chip_config.spirx[4] */
#define NDP120_CHIP_CONFIG_SPIRX(i) (0x40009050U + ((i) << 2))
#define NDP120_CHIP_CONFIG_SPIRX_COUNT 4
#define NDP120_CHIP_CONFIG_SPIRX_RXBYTES_SHIFT 0
#define NDP120_CHIP_CONFIG_SPIRX_RXBYTES_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_SPIRX_RXBYTES(v) \
        ((v) << NDP120_CHIP_CONFIG_SPIRX_RXBYTES_SHIFT)
#define NDP120_CHIP_CONFIG_SPIRX_RXBYTES_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPIRX_RXBYTES_SHIFT))
#define NDP120_CHIP_CONFIG_SPIRX_RXBYTES_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPIRX_RXBYTES_MASK) | ((v) << NDP120_CHIP_CONFIG_SPIRX_RXBYTES_SHIFT))
#define NDP120_CHIP_CONFIG_SPIRX_RXBYTES_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPIRX_RXBYTES_MASK) >> NDP120_CHIP_CONFIG_SPIRX_RXBYTES_SHIFT)
/* register ndp120.chip_config.i2ccfg0 */
#define NDP120_CHIP_CONFIG_I2CCFG0 0x40009060U
#define NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_SHIFT 0
#define NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_MASK) >> NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_ENABLE_INTERFACE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_SHIFT 1
#define NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_MASK) >> NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_CLK_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CCFG0_RESET_SHIFT 2
#define NDP120_CHIP_CONFIG_I2CCFG0_RESET_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_I2CCFG0_RESET(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CCFG0_RESET_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_RESET_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_RESET_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_RESET_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CCFG0_RESET_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_RESET_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_RESET_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CCFG0_RESET_MASK) >> NDP120_CHIP_CONFIG_I2CCFG0_RESET_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_RESET_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_SHIFT 3
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_MASK 0x00000018U
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_MASK) >> NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_DISABLE 0x0U
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_PULLUP 0x1U
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_PULLUP_HIGH 0x2U
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_DRIVE 0x3U
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_MAX 0x3U
#define NDP120_CHIP_CONFIG_I2CCFG0_PULLUP_MODE_VALID(v) \
        (v >= 0 && v <= 3)
#define NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_SHIFT 5
#define NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_MASK 0x00000060U
#define NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_MASK) >> NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_SCL_DRIVE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_SHIFT 7
#define NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_MASK 0x00000180U
#define NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_MASK) >> NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_SDA_DRIVE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_SHIFT 9
#define NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_MASK 0x00000200U
#define NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_MASK) >> NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_HW_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_SHIFT 10
#define NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_MASK 0x00000400U
#define NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_MASK) >> NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_INT_MASK_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_SHIFT 11
#define NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_MASK 0x00000800U
#define NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_SHIFT))
#define NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_MASK) >> NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_SHIFT)
#define NDP120_CHIP_CONFIG_I2CCFG0_TIMEOUT_CLEAR_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CCFG0_DEFAULT 0x00000008U 
/* register ndp120.chip_config.i2csts0 */
#define NDP120_CHIP_CONFIG_I2CSTS0 0x40009064U
#define NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE_SHIFT 0
#define NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE_MASK) >> NDP120_CHIP_CONFIG_I2CSTS0_CMD_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE_SHIFT 1
#define NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE_MASK 0x00000006U
#define NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE_MASK) >> NDP120_CHIP_CONFIG_I2CSTS0_BUS_STATE_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS_SHIFT 3
#define NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS_MASK 0x00000078U
#define NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS_MASK) >> NDP120_CHIP_CONFIG_I2CSTS0_PACKET_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT_SHIFT 7
#define NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT_MASK 0x00000780U
#define NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT_MASK) >> NDP120_CHIP_CONFIG_I2CSTS0_DATA_COUNT_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR_SHIFT 11
#define NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR_MASK 0x0003f800U
#define NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR_MASK) >> NDP120_CHIP_CONFIG_I2CSTS0_REG_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET_SHIFT 18
#define NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET_MASK 0x00040000U
#define NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET_MASK) >> NDP120_CHIP_CONFIG_I2CSTS0_WRITE_PACKET_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET_SHIFT 19
#define NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET_MASK 0x00080000U
#define NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET_MASK) >> NDP120_CHIP_CONFIG_I2CSTS0_READ_PACKET_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG_SHIFT 20
#define NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG_MASK 0x00100000U
#define NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG_MASK) >> NDP120_CHIP_CONFIG_I2CSTS0_TIMEOUT_FLAG_SHIFT)
/* register ndp120.chip_config.i2ctimeout */
#define NDP120_CHIP_CONFIG_I2CTIMEOUT 0x40009068U
#define NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_SHIFT 0
#define NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_MASK 0x0003ffffU
#define NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_SHIFT)
#define NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_SHIFT))
#define NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_SHIFT))
#define NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_MASK) >> NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_SHIFT)
#define NDP120_CHIP_CONFIG_I2CTIMEOUT_TIMEOUT_DEFAULT 0x00004e20U
#define NDP120_CHIP_CONFIG_I2CTIMEOUT_DEFAULT 0x00004e20U 
/* register ndp120.chip_config.i2cshadowcr */
#define NDP120_CHIP_CONFIG_I2CSHADOWCR 0x4000906cU
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_SHIFT 0
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_RW(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_RW_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_SHIFT 1
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_MS(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_MS_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_SHIFT 2
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_NEA_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_SHIFT 3
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_ACKEN_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_SHIFT 4
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_MASK 0x00000010U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_HOLD_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_SHIFT 5
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_MASK 0x00000020U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_SLVMON_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_SHIFT 6
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_MASK 0x00000040U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_CLRFIFO_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_SHIFT 8
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_MASK 0x00003f00U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_A_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_SHIFT 14
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_MASK 0x0000c000U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DIV_B_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWCR_DEFAULT 0x0000004cU 
/* register ndp120.chip_config.i2cshadowar */
#define NDP120_CHIP_CONFIG_I2CSHADOWAR 0x40009070U
#define NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_SHIFT 0
#define NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_MASK 0x000003ffU
#define NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWAR_ADDR_DEFAULT 0x00000050U
#define NDP120_CHIP_CONFIG_I2CSHADOWAR_DEFAULT 0x00000050U 
/* register ndp120.chip_config.i2cshadowier */
#define NDP120_CHIP_CONFIG_I2CSHADOWIER 0x40009074U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_SHIFT 0
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_COMP_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_SHIFT 1
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_DATA_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_SHIFT 2
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_NACK_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_SHIFT 3
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TO(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TO_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_SHIFT 4
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_MASK 0x00000010U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_SLV_RDY_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_SHIFT 5
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_MASK 0x00000020U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_OVF_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_SHIFT 6
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_MASK 0x00000040U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_TX_OVF_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_SHIFT 7
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_MASK 0x00000080U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_RX_UNF_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_SHIFT 9
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_MASK 0x00000200U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_ARB_LOST_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWIER_DEFAULT 0x00000003U 
/* register ndp120.chip_config.i2cshadowgfcr */
#define NDP120_CHIP_CONFIG_I2CSHADOWGFCR 0x40009078U
#define NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_SHIFT 0
#define NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_MASK 0x0000000fU
#define NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH(v) \
        ((v) << NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_MASK) | ((v) << NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_SHIFT))
#define NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_MASK) >> NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_SHIFT)
#define NDP120_CHIP_CONFIG_I2CSHADOWGFCR_GFILTER_DEPTH_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_I2CSHADOWGFCR_DEFAULT 0x00000000U 
/* register ndp120.chip_config.hostint */
#define NDP120_CHIP_CONFIG_HOSTINT 0x4000907cU
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT_SHIFT 0
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT(v) \
        ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT_MASK) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT_MASK) >> NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MATCH_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT_SHIFT 1
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT(v) \
        ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT_MASK) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT_MASK) >> NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBIN_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT_SHIFT 2
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT(v) \
        ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT_MASK) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT_MASK) >> NDP120_CHIP_CONFIG_HOSTINT_CLEAR_MBOUT_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT_SHIFT 3
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT(v) \
        ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT_MASK) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT_MASK) >> NDP120_CHIP_CONFIG_HOSTINT_CLEAR_DNN_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT_SHIFT 4
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT_MASK 0x00000010U
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT(v) \
        ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT_MASK) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT_MASK) >> NDP120_CHIP_CONFIG_HOSTINT_CLEAR_FREQ_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT_SHIFT 5
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT_MASK 0x00000020U
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT(v) \
        ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT_MASK) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT_MASK) >> NDP120_CHIP_CONFIG_HOSTINT_CLEAR_AE_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT_SHIFT 6
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT_MASK 0x00000040U
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT(v) \
        ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT_MASK) | ((v) << NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT_MASK) >> NDP120_CHIP_CONFIG_HOSTINT_CLEAR_WM_INT_SHIFT)
/* register ndp120.chip_config.mboxin */
#define NDP120_CHIP_CONFIG_MBOXIN 0x40009080U
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_SHIFT 0
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_MASK 0x000000ffU
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN(v) \
        ((v) << NDP120_CHIP_CONFIG_MBOXIN_MBIN_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBOXIN_MBIN_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBOXIN_MBIN_MASK) | ((v) << NDP120_CHIP_CONFIG_MBOXIN_MBIN_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBOXIN_MBIN_MASK) >> NDP120_CHIP_CONFIG_MBOXIN_MBIN_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE_SHIFT 8
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE_MASK 0x00000100U
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE(v) \
        ((v) << NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE_MASK) | ((v) << NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE_MASK) >> NDP120_CHIP_CONFIG_MBOXIN_MBIN_TOGGLE_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_SHIFT 16
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_MASK 0x00ff0000U
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP(v) \
        ((v) << NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_MASK) | ((v) << NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_MASK) >> NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXIN_MBIN_RESP_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBOXIN_DEFAULT 0x00000000U 
/* register ndp120.chip_config.mboxout */
#define NDP120_CHIP_CONFIG_MBOXOUT 0x40009084U
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_SHIFT 0
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_MASK 0x000000ffU
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT(v) \
        ((v) << NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_MASK) | ((v) << NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_MASK) >> NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_SHIFT 16
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_MASK 0x00ff0000U
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP(v) \
        ((v) << NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_MASK) | ((v) << NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_MASK) >> NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE_SHIFT 24
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE_MASK 0x01000000U
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE(v) \
        ((v) << NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE_MASK) | ((v) << NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE_SHIFT))
#define NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE_MASK) >> NDP120_CHIP_CONFIG_MBOXOUT_MBOUT_RESP_TOGGLE_SHIFT)
#define NDP120_CHIP_CONFIG_MBOXOUT_DEFAULT 0x00000000U 
/* register ndp120.chip_config.matchint */
#define NDP120_CHIP_CONFIG_MATCHINT 0x40009088U
#define NDP120_CHIP_CONFIG_MATCHINT_STATUS_SHIFT 0
#define NDP120_CHIP_CONFIG_MATCHINT_STATUS_MASK 0x000000ffU
#define NDP120_CHIP_CONFIG_MATCHINT_STATUS(v) \
        ((v) << NDP120_CHIP_CONFIG_MATCHINT_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_MATCHINT_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MATCHINT_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_MATCHINT_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MATCHINT_STATUS_MASK) | ((v) << NDP120_CHIP_CONFIG_MATCHINT_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_MATCHINT_STATUS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MATCHINT_STATUS_MASK) >> NDP120_CHIP_CONFIG_MATCHINT_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_MATCHINT_STATUS_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MATCHINT_DEFAULT 0x00000000U 
/* register ndp120.chip_config.featureint */
#define NDP120_CHIP_CONFIG_FEATUREINT 0x4000908cU
#define NDP120_CHIP_CONFIG_FEATUREINT_STATUS_SHIFT 0
#define NDP120_CHIP_CONFIG_FEATUREINT_STATUS_MASK 0x000000ffU
#define NDP120_CHIP_CONFIG_FEATUREINT_STATUS(v) \
        ((v) << NDP120_CHIP_CONFIG_FEATUREINT_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_FEATUREINT_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FEATUREINT_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_FEATUREINT_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FEATUREINT_STATUS_MASK) | ((v) << NDP120_CHIP_CONFIG_FEATUREINT_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_FEATUREINT_STATUS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FEATUREINT_STATUS_MASK) >> NDP120_CHIP_CONFIG_FEATUREINT_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_FEATUREINT_STATUS_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_FEATUREINT_DEFAULT 0x00000000U 
/* register ndp120.chip_config.dnnint */
#define NDP120_CHIP_CONFIG_DNNINT 0x40009090U
#define NDP120_CHIP_CONFIG_DNNINT_STATUS_SHIFT 0
#define NDP120_CHIP_CONFIG_DNNINT_STATUS_MASK 0x000000ffU
#define NDP120_CHIP_CONFIG_DNNINT_STATUS(v) \
        ((v) << NDP120_CHIP_CONFIG_DNNINT_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_DNNINT_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DNNINT_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_DNNINT_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DNNINT_STATUS_MASK) | ((v) << NDP120_CHIP_CONFIG_DNNINT_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_DNNINT_STATUS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DNNINT_STATUS_MASK) >> NDP120_CHIP_CONFIG_DNNINT_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_DNNINT_STATUS_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_DNNINT_DEFAULT 0x00000000U 
/* register ndp120.chip_config.watermarkint */
#define NDP120_CHIP_CONFIG_WATERMARKINT 0x40009094U
#define NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_SHIFT 0
#define NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_WATERMARKINT_STATUS(v) \
        ((v) << NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_MASK) | ((v) << NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_MASK) >> NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_WATERMARKINT_STATUS_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_WATERMARKINT_DEFAULT 0x00000000U 
/* register ndp120.chip_config.mcu_int_to_dsp */
#define NDP120_CHIP_CONFIG_MCU_INT_TO_DSP 0x40009098U
#define NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_SHIFT 0
#define NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA(v) \
        ((v) << NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_MASK) | ((v) << NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_MASK) >> NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_MCU_INT_DATA_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MCU_INT_TO_DSP_DEFAULT 0x00000000U 
/* register ndp120.chip_config.dsp_int_to_mcu */
#define NDP120_CHIP_CONFIG_DSP_INT_TO_MCU 0x4000909cU
#define NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_SHIFT 0
#define NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_MASK) >> NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DSP_INT_DATA_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_DSP_INT_TO_MCU_DEFAULT 0x00000000U 
/* register ndp120.chip_config.mem */
#define NDP120_CHIP_CONFIG_MEM 0x400090a0U
#define NDP120_CHIP_CONFIG_MEM_MARGIN_READ_SHIFT 0
#define NDP120_CHIP_CONFIG_MEM_MARGIN_READ_MASK 0x00000007U
#define NDP120_CHIP_CONFIG_MEM_MARGIN_READ(v) \
        ((v) << NDP120_CHIP_CONFIG_MEM_MARGIN_READ_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_MARGIN_READ_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MEM_MARGIN_READ_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_MARGIN_READ_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MEM_MARGIN_READ_MASK) | ((v) << NDP120_CHIP_CONFIG_MEM_MARGIN_READ_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_MARGIN_READ_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MEM_MARGIN_READ_MASK) >> NDP120_CHIP_CONFIG_MEM_MARGIN_READ_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_MARGIN_READ_DEFAULT 0x00000007U
#define NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_SHIFT 3
#define NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_MASK 0x00000018U
#define NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE(v) \
        ((v) << NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_MASK) | ((v) << NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_MASK) >> NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_MARGIN_WRITE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MEM_READ_ASSIST_SHIFT 5
#define NDP120_CHIP_CONFIG_MEM_READ_ASSIST_MASK 0x000000e0U
#define NDP120_CHIP_CONFIG_MEM_READ_ASSIST(v) \
        ((v) << NDP120_CHIP_CONFIG_MEM_READ_ASSIST_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_READ_ASSIST_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MEM_READ_ASSIST_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_READ_ASSIST_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MEM_READ_ASSIST_MASK) | ((v) << NDP120_CHIP_CONFIG_MEM_READ_ASSIST_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_READ_ASSIST_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MEM_READ_ASSIST_MASK) >> NDP120_CHIP_CONFIG_MEM_READ_ASSIST_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_READ_ASSIST_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_SHIFT 8
#define NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_MASK 0x00000700U
#define NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST(v) \
        ((v) << NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_MASK) | ((v) << NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_MASK) >> NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_WRITE_ASSIST_DEFAULT 0x00000007U
#define NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_SHIFT 11
#define NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_MASK 0x00003800U
#define NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM(v) \
        ((v) << NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_MASK) | ((v) << NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_MASK) >> NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_PG_BOOTRAM_DEFAULT 0x00000006U
#define NDP120_CHIP_CONFIG_MEM_PG_RAM_SHIFT 14
#define NDP120_CHIP_CONFIG_MEM_PG_RAM_MASK 0x0001c000U
#define NDP120_CHIP_CONFIG_MEM_PG_RAM(v) \
        ((v) << NDP120_CHIP_CONFIG_MEM_PG_RAM_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_PG_RAM_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MEM_PG_RAM_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_PG_RAM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MEM_PG_RAM_MASK) | ((v) << NDP120_CHIP_CONFIG_MEM_PG_RAM_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_PG_RAM_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MEM_PG_RAM_MASK) >> NDP120_CHIP_CONFIG_MEM_PG_RAM_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_PG_RAM_DEFAULT 0x00000006U
#define NDP120_CHIP_CONFIG_MEM_PG_ROM_SHIFT 17
#define NDP120_CHIP_CONFIG_MEM_PG_ROM_MASK 0x00020000U
#define NDP120_CHIP_CONFIG_MEM_PG_ROM(v) \
        ((v) << NDP120_CHIP_CONFIG_MEM_PG_ROM_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_PG_ROM_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MEM_PG_ROM_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_PG_ROM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MEM_PG_ROM_MASK) | ((v) << NDP120_CHIP_CONFIG_MEM_PG_ROM_SHIFT))
#define NDP120_CHIP_CONFIG_MEM_PG_ROM_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MEM_PG_ROM_MASK) >> NDP120_CHIP_CONFIG_MEM_PG_ROM_SHIFT)
#define NDP120_CHIP_CONFIG_MEM_PG_ROM_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MEM_DEFAULT 0x0001b707U 
/* register ndp120.chip_config.addrprotlo_0 */
#define NDP120_CHIP_CONFIG_ADDRPROTLO_0 0x400090a4U
/* register ndp120.chip_config.addrprothi_0 */
#define NDP120_CHIP_CONFIG_ADDRPROTHI_0 0x400090a8U
/* register ndp120.chip_config.addrprotlo_1 */
#define NDP120_CHIP_CONFIG_ADDRPROTLO_1 0x400090acU
/* register ndp120.chip_config.addrprothi_1 */
#define NDP120_CHIP_CONFIG_ADDRPROTHI_1 0x400090b0U
/* register ndp120.chip_config.otpctl */
#define NDP120_CHIP_CONFIG_OTPCTL 0x400090b4U
#define NDP120_CHIP_CONFIG_OTPCTL_READ_SHIFT 0
#define NDP120_CHIP_CONFIG_OTPCTL_READ_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_OTPCTL_READ(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_READ_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_READ_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_READ_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_READ_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_READ_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_READ_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_READ_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_READ_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_READ_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_READ_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCTL_READNEXT_SHIFT 1
#define NDP120_CHIP_CONFIG_OTPCTL_READNEXT_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_OTPCTL_READNEXT(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_READNEXT_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_READNEXT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_READNEXT_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_READNEXT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_READNEXT_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_READNEXT_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_READNEXT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_READNEXT_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_READNEXT_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_READNEXT_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCTL_PROG_SHIFT 2
#define NDP120_CHIP_CONFIG_OTPCTL_PROG_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_OTPCTL_PROG(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_PROG_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_PROG_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_PROG_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_PROG_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_PROG_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_PROG_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_PROG_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_PROG_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_PROG_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_PROG_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCTL_PWDN_SHIFT 3
#define NDP120_CHIP_CONFIG_OTPCTL_PWDN_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_OTPCTL_PWDN(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_PWDN_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_PWDN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_PWDN_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_PWDN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_PWDN_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_PWDN_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_PWDN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_PWDN_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_PWDN_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_PWDN_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_SHIFT 4
#define NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_MASK 0x000000f0U
#define NDP120_CHIP_CONFIG_OTPCTL_WORDADDR(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_WORDADDR_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCTL_BITADDR_SHIFT 8
#define NDP120_CHIP_CONFIG_OTPCTL_BITADDR_MASK 0x00001f00U
#define NDP120_CHIP_CONFIG_OTPCTL_BITADDR(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_BITADDR_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_BITADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_BITADDR_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_BITADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_BITADDR_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_BITADDR_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_BITADDR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_BITADDR_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_BITADDR_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_BITADDR_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCTL_DONE_SHIFT 13
#define NDP120_CHIP_CONFIG_OTPCTL_DONE_MASK 0x00002000U
#define NDP120_CHIP_CONFIG_OTPCTL_DONE(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_DONE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_DONE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_DONE_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_DONE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_DONE_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_SHIFT 14
#define NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_MASK 0x00004000U
#define NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_CLEARDONE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE_SHIFT 15
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE_MASK 0x00008000U
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_LOCK_DEVICE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_SHIFT 16
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_MASK 0x00010000U
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_DISABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_SHIFT 17
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_MASK 0x00020000U
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_LOCK_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_SHIFT 18
#define NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_MASK 0x00040000U
#define NDP120_CHIP_CONFIG_OTPCTL_OTP_PU(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_OTP_PU_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_SHIFT 19
#define NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_MASK 0x00080000U
#define NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_RD_STRETCH_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCTL_STATUS_SHIFT 20
#define NDP120_CHIP_CONFIG_OTPCTL_STATUS_MASK 0x0ff00000U
#define NDP120_CHIP_CONFIG_OTPCTL_STATUS(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCTL_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCTL_STATUS_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCTL_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCTL_STATUS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCTL_STATUS_MASK) >> NDP120_CHIP_CONFIG_OTPCTL_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCTL_DEFAULT 0x00000000U 
/* register ndp120.chip_config.otpcfg */
#define NDP120_CHIP_CONFIG_OTPCFG 0x400090b8U
#define NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_SHIFT 0
#define NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_MASK 0x000000ffU
#define NDP120_CHIP_CONFIG_OTPCFG_WAKEUP(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_MASK) >> NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCFG_WAKEUP_DEFAULT 0x0000000bU
#define NDP120_CHIP_CONFIG_OTPCFG_STROBE_SHIFT 8
#define NDP120_CHIP_CONFIG_OTPCFG_STROBE_MASK 0x0000ff00U
#define NDP120_CHIP_CONFIG_OTPCFG_STROBE(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCFG_STROBE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCFG_STROBE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCFG_STROBE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCFG_STROBE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCFG_STROBE_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCFG_STROBE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCFG_STROBE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCFG_STROBE_MASK) >> NDP120_CHIP_CONFIG_OTPCFG_STROBE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCFG_STROBE_DEFAULT 0x00000050U
#define NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_SHIFT 16
#define NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_MASK 0xffff0000U
#define NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE(v) \
        ((v) << NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_MASK) | ((v) << NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_SHIFT))
#define NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_MASK) >> NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_SHIFT)
#define NDP120_CHIP_CONFIG_OTPCFG_DEVICE_ID_OVERRIDE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_OTPCFG_DEFAULT 0x0000500bU 
/* register ndp120.chip_config.otpdout */
#define NDP120_CHIP_CONFIG_OTPDOUT 0x400090bcU
/* register ndp120.chip_config.otpprotkey */
#define NDP120_CHIP_CONFIG_OTPPROTKEY 0x400090c0U
/* register ndp120.chip_config.fllctl0 */
#define NDP120_CHIP_CONFIG_FLLCTL0 0x400090c4U
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_SHIFT 0
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_OSC_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_SHIFT 1
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_SHIFT 2
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLETRACKING_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_SHIFT 3
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_ENABLESIGMADELTA_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_SHIFT 4
#define NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_MASK 0x00000070U
#define NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_PERIODGAIN_DEFAULT 0x00000003U
#define NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_SHIFT 7
#define NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_MASK 0x00000380U
#define NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_COARSECODE_DEFAULT 0x00000007U
#define NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_SHIFT 10
#define NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_MASK 0x007ffc00U
#define NDP120_CHIP_CONFIG_FLLCTL0_FINECODE(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_FINECODE_DEFAULT 0x00001f80U
#define NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_SHIFT 23
#define NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_MASK 0x03800000U
#define NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_MAXCOARSE_DEFAULT 0x00000007U
#define NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_SHIFT 26
#define NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_MASK 0x04000000U
#define NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_CODE_UPDATE_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_SHIFT 27
#define NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_MASK 0x08000000U
#define NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_MULT_UPDATE_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_SHIFT 28
#define NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_MASK 0x10000000U
#define NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_CLK_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_FLLCTL0_RSTB_SHIFT 29
#define NDP120_CHIP_CONFIG_FLLCTL0_RSTB_MASK 0x20000000U
#define NDP120_CHIP_CONFIG_FLLCTL0_RSTB(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL0_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_RSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_RSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL0_RSTB_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL0_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL0_RSTB_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL0_RSTB_MASK) >> NDP120_CHIP_CONFIG_FLLCTL0_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL0_RSTB_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_FLLCTL0_DEFAULT 0x2ffe03b9U 
/* register ndp120.chip_config.fllctl1 */
#define NDP120_CHIP_CONFIG_FLLCTL1 0x400090c8U
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_SHIFT 0
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_MASK 0x00003fffU
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_MASK) >> NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQMULT_DEFAULT 0x000007d0U
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_SHIFT 14
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_MASK 0x0fffc000U
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_MASK) >> NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL1_FREQDIV_DEFAULT 0x00000042U
#define NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_SHIFT 28
#define NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_MASK 0xf0000000U
#define NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_MASK) >> NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL1_WARMUPLIMIT_DEFAULT 0x00000004U
#define NDP120_CHIP_CONFIG_FLLCTL1_DEFAULT 0x401087d0U 
/* register ndp120.chip_config.fllctl2 */
#define NDP120_CHIP_CONFIG_FLLCTL2 0x400090ccU
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_SHIFT 0
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_MASK 0x000000ffU
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_MASK) >> NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKLIMIT_DEFAULT 0x00000010U
#define NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_SHIFT 8
#define NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_MASK 0x0000ff00U
#define NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_MASK) >> NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL2_UNLOCKLIMIT_DEFAULT 0x00000010U
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_SHIFT 16
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_MASK 0x000f0000U
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_MASK) >> NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL2_LOCKCOUNT_DEFAULT 0x0000000fU
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_SHIFT 20
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_MASK 0x00f00000U
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_MASK) >> NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN0_DEFAULT 0x00000007U
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_SHIFT 24
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_MASK 0x0f000000U
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_MASK) >> NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL2_LOOPGAIN1_DEFAULT 0x00000009U
#define NDP120_CHIP_CONFIG_FLLCTL2_DEFAULT 0x097f1010U 
/* register ndp120.chip_config.fllctl3 */
#define NDP120_CHIP_CONFIG_FLLCTL3 0x400090d0U
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_SHIFT 0
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_MASK 0x000003ffU
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_MASK) >> NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOOFFSET_DEFAULT 0x00000034U
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_SHIFT 10
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_MASK 0x000ffc00U
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_MASK) >> NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL3_DCOCOARSEDELAY_DEFAULT 0x00000050U
#define NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_SHIFT 20
#define NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_MASK 0x03f00000U
#define NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_MASK) >> NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL3_FINELOWERLIMIT_DEFAULT 0x00000010U
#define NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_SHIFT 26
#define NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_MASK 0xfc000000U
#define NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_SHIFT))
#define NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_MASK) >> NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_SHIFT)
#define NDP120_CHIP_CONFIG_FLLCTL3_FINEUPPERLIMIT_DEFAULT 0x00000030U
#define NDP120_CHIP_CONFIG_FLLCTL3_DEFAULT 0xc1014034U 
/* register ndp120.chip_config.fllsts0 */
#define NDP120_CHIP_CONFIG_FLLSTS0 0x400090d4U
#define NDP120_CHIP_CONFIG_FLLSTS0_MODE_SHIFT 0
#define NDP120_CHIP_CONFIG_FLLSTS0_MODE_MASK 0x00000007U
#define NDP120_CHIP_CONFIG_FLLSTS0_MODE(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLSTS0_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS0_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLSTS0_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS0_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLSTS0_MODE_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLSTS0_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS0_MODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLSTS0_MODE_MASK) >> NDP120_CHIP_CONFIG_FLLSTS0_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS0_LOCKED_SHIFT 3
#define NDP120_CHIP_CONFIG_FLLSTS0_LOCKED_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_FLLSTS0_LOCKED(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLSTS0_LOCKED_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS0_LOCKED_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLSTS0_LOCKED_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS0_LOCKED_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLSTS0_LOCKED_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLSTS0_LOCKED_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS0_LOCKED_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLSTS0_LOCKED_MASK) >> NDP120_CHIP_CONFIG_FLLSTS0_LOCKED_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK_SHIFT 4
#define NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK_MASK 0x00000ff0U
#define NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK_MASK) >> NDP120_CHIP_CONFIG_FLLSTS0_NUMUNLOCK_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR_SHIFT 12
#define NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR_MASK 0x07fff000U
#define NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR_MASK) >> NDP120_CHIP_CONFIG_FLLSTS0_PERIODERROR_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL_SHIFT 27
#define NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL_MASK 0x38000000U
#define NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL_MASK) >> NDP120_CHIP_CONFIG_FLLSTS0_DCOCSEL_SHIFT)
/* register ndp120.chip_config.fllsts1 */
#define NDP120_CHIP_CONFIG_FLLSTS1 0x400090d8U
#define NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR_SHIFT 0
#define NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR_MASK 0x00000fffU
#define NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR_MASK) >> NDP120_CHIP_CONFIG_FLLSTS1_AVGPERIODERROR_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR_SHIFT 12
#define NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR_MASK 0xfffff000U
#define NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR(v) \
        ((v) << NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR_SHIFT)
#define NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR_MASK) | ((v) << NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR_SHIFT))
#define NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR_MASK) >> NDP120_CHIP_CONFIG_FLLSTS1_INTEGRATOR_SHIFT)
/* register ndp120.chip_config.fllsts2 */
#define NDP120_CHIP_CONFIG_FLLSTS2 0x400090dcU
/* register ndp120.chip_config.fllsts3 */
#define NDP120_CHIP_CONFIG_FLLSTS3 0x400090e0U
/* register ndp120.chip_config.crcctl */
#define NDP120_CHIP_CONFIG_CRCCTL 0x400090e4U
#define NDP120_CHIP_CONFIG_CRCCTL_INIT_SHIFT 0
#define NDP120_CHIP_CONFIG_CRCCTL_INIT_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_CRCCTL_INIT(v) \
        ((v) << NDP120_CHIP_CONFIG_CRCCTL_INIT_SHIFT)
#define NDP120_CHIP_CONFIG_CRCCTL_INIT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CRCCTL_INIT_SHIFT))
#define NDP120_CHIP_CONFIG_CRCCTL_INIT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CRCCTL_INIT_MASK) | ((v) << NDP120_CHIP_CONFIG_CRCCTL_INIT_SHIFT))
#define NDP120_CHIP_CONFIG_CRCCTL_INIT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CRCCTL_INIT_MASK) >> NDP120_CHIP_CONFIG_CRCCTL_INIT_SHIFT)
#define NDP120_CHIP_CONFIG_CRCCTL_INIT_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_SHIFT 1
#define NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_MASK 0x00000006U
#define NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES(v) \
        ((v) << NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_SHIFT)
#define NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_SHIFT))
#define NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_MASK) | ((v) << NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_SHIFT))
#define NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_MASK) >> NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_SHIFT)
#define NDP120_CHIP_CONFIG_CRCCTL_NUMBYTES_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CRCCTL_DEFAULT 0x00000000U 
/* register ndp120.chip_config.crcin */
#define NDP120_CHIP_CONFIG_CRCIN 0x400090e8U
#define NDP120_CHIP_CONFIG_CRCIN_WORD_SHIFT 0
#define NDP120_CHIP_CONFIG_CRCIN_WORD_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_CRCIN_WORD(v) \
        ((v) << NDP120_CHIP_CONFIG_CRCIN_WORD_SHIFT)
#define NDP120_CHIP_CONFIG_CRCIN_WORD_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CRCIN_WORD_SHIFT))
#define NDP120_CHIP_CONFIG_CRCIN_WORD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CRCIN_WORD_MASK) | ((v) << NDP120_CHIP_CONFIG_CRCIN_WORD_SHIFT))
#define NDP120_CHIP_CONFIG_CRCIN_WORD_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CRCIN_WORD_MASK) >> NDP120_CHIP_CONFIG_CRCIN_WORD_SHIFT)
#define NDP120_CHIP_CONFIG_CRCIN_WORD_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CRCIN_DEFAULT 0x00000000U 
/* register ndp120.chip_config.crcout */
#define NDP120_CHIP_CONFIG_CRCOUT 0x400090ecU
#define NDP120_CHIP_CONFIG_CRCOUT_WORD_SHIFT 0
#define NDP120_CHIP_CONFIG_CRCOUT_WORD_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_CRCOUT_WORD(v) \
        ((v) << NDP120_CHIP_CONFIG_CRCOUT_WORD_SHIFT)
#define NDP120_CHIP_CONFIG_CRCOUT_WORD_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CRCOUT_WORD_SHIFT))
#define NDP120_CHIP_CONFIG_CRCOUT_WORD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CRCOUT_WORD_MASK) | ((v) << NDP120_CHIP_CONFIG_CRCOUT_WORD_SHIFT))
#define NDP120_CHIP_CONFIG_CRCOUT_WORD_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CRCOUT_WORD_MASK) >> NDP120_CHIP_CONFIG_CRCOUT_WORD_SHIFT)
/* register ndp120.chip_config.aesctl */
#define NDP120_CHIP_CONFIG_AESCTL 0x400090f0U
#define NDP120_CHIP_CONFIG_AESCTL_ENABLE_SHIFT 0
#define NDP120_CHIP_CONFIG_AESCTL_ENABLE_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_AESCTL_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_AESCTL_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AESCTL_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AESCTL_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_AESCTL_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AESCTL_ENABLE_MASK) >> NDP120_CHIP_CONFIG_AESCTL_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_SHIFT 1
#define NDP120_CHIP_CONFIG_AESCTL_MODE_MASK 0x0000001eU
#define NDP120_CHIP_CONFIG_AESCTL_MODE(v) \
        ((v) << NDP120_CHIP_CONFIG_AESCTL_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AESCTL_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AESCTL_MODE_MASK) | ((v) << NDP120_CHIP_CONFIG_AESCTL_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_MODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AESCTL_MODE_MASK) >> NDP120_CHIP_CONFIG_AESCTL_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_MODE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_L2_KEY 0x0U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_L3_KEY 0x1U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_NONCE 0x2U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_DECRYPT 0x3U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_DECRYPT_TAG 0x4U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_CALC_TAG_FIRST 0x5U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_CALC_TAG 0x6U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_AES_KEY 0x7U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_AES_ECB 0x8U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_MAX 0x8U
#define NDP120_CHIP_CONFIG_AESCTL_MODE_VALID(v) \
        (v >= 0 && v <= 8)
#define NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_SHIFT 5
#define NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_MASK 0x000000e0U
#define NDP120_CHIP_CONFIG_AESCTL_KEY_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_MASK) >> NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_KEY_SEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AESCTL_PGEN_SHIFT 8
#define NDP120_CHIP_CONFIG_AESCTL_PGEN_MASK 0x00000100U
#define NDP120_CHIP_CONFIG_AESCTL_PGEN(v) \
        ((v) << NDP120_CHIP_CONFIG_AESCTL_PGEN_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_PGEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AESCTL_PGEN_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_PGEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AESCTL_PGEN_MASK) | ((v) << NDP120_CHIP_CONFIG_AESCTL_PGEN_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_PGEN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AESCTL_PGEN_MASK) >> NDP120_CHIP_CONFIG_AESCTL_PGEN_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_PGEN_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS_SHIFT 9
#define NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS_MASK 0x00001e00U
#define NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS(v) \
        ((v) << NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS_MASK) | ((v) << NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS_MASK) >> NDP120_CHIP_CONFIG_AESCTL_KEY_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_SHIFT 13
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_MASK 0x0001e000U
#define NDP120_CHIP_CONFIG_AESCTL_STATUS(v) \
        ((v) << NDP120_CHIP_CONFIG_AESCTL_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AESCTL_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AESCTL_STATUS_MASK) | ((v) << NDP120_CHIP_CONFIG_AESCTL_STATUS_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AESCTL_STATUS_MASK) >> NDP120_CHIP_CONFIG_AESCTL_STATUS_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_L2_READY 0x1U
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_L3_READY 0x2U
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_DECRYPT 0x3U
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_TAG 0x5U
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_ECB_KEY_READY 0x6U
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_ENCRYPT 0x7U
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_ERROR 0x8U
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_MAX 0x8U
#define NDP120_CHIP_CONFIG_AESCTL_STATUS_VALID(v) \
        (v == NDP120_CHIP_CONFIG_AESCTL_STATUS_L2_READY || v == NDP120_CHIP_CONFIG_AESCTL_STATUS_L3_READY || v == NDP120_CHIP_CONFIG_AESCTL_STATUS_DECRYPT || v == NDP120_CHIP_CONFIG_AESCTL_STATUS_TAG || v == NDP120_CHIP_CONFIG_AESCTL_STATUS_ECB_KEY_READY || v == NDP120_CHIP_CONFIG_AESCTL_STATUS_ENCRYPT || v == NDP120_CHIP_CONFIG_AESCTL_STATUS_ERROR)
#define NDP120_CHIP_CONFIG_AESCTL_RUNNING_SHIFT 17
#define NDP120_CHIP_CONFIG_AESCTL_RUNNING_MASK 0x00020000U
#define NDP120_CHIP_CONFIG_AESCTL_RUNNING(v) \
        ((v) << NDP120_CHIP_CONFIG_AESCTL_RUNNING_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_RUNNING_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AESCTL_RUNNING_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_RUNNING_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AESCTL_RUNNING_MASK) | ((v) << NDP120_CHIP_CONFIG_AESCTL_RUNNING_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_RUNNING_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AESCTL_RUNNING_MASK) >> NDP120_CHIP_CONFIG_AESCTL_RUNNING_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_DONE_SHIFT 18
#define NDP120_CHIP_CONFIG_AESCTL_DONE_MASK 0x00040000U
#define NDP120_CHIP_CONFIG_AESCTL_DONE(v) \
        ((v) << NDP120_CHIP_CONFIG_AESCTL_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_DONE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AESCTL_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_DONE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AESCTL_DONE_MASK) | ((v) << NDP120_CHIP_CONFIG_AESCTL_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_DONE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AESCTL_DONE_MASK) >> NDP120_CHIP_CONFIG_AESCTL_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_RSTB_SHIFT 19
#define NDP120_CHIP_CONFIG_AESCTL_RSTB_MASK 0x00080000U
#define NDP120_CHIP_CONFIG_AESCTL_RSTB(v) \
        ((v) << NDP120_CHIP_CONFIG_AESCTL_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_RSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_AESCTL_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_RSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_AESCTL_RSTB_MASK) | ((v) << NDP120_CHIP_CONFIG_AESCTL_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_AESCTL_RSTB_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_AESCTL_RSTB_MASK) >> NDP120_CHIP_CONFIG_AESCTL_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_AESCTL_RSTB_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_AESCTL_DEFAULT 0x00080000U 
/* register array ndp120.chip_config.aesdin[4] */
#define NDP120_CHIP_CONFIG_AESDIN(i) (0x400090f4U + ((i) << 2))
#define NDP120_CHIP_CONFIG_AESDIN_COUNT 4
/* register array ndp120.chip_config.aesdout[4] */
#define NDP120_CHIP_CONFIG_AESDOUT(i) (0x40009104U + ((i) << 2))
#define NDP120_CHIP_CONFIG_AESDOUT_COUNT 4
/* register ndp120.chip_config.spi_cfg */
#define NDP120_CHIP_CONFIG_SPI_CFG 0x40009114U
#define NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_SHIFT 0
#define NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_SPI_CFG_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_MASK) >> NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_SPI_CFG_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_SHIFT 1
#define NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_MASK 0xfffffffeU
#define NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE(v) \
        ((v) << NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_SHIFT)
#define NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_SHIFT))
#define NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_MASK) | ((v) << NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_SHIFT))
#define NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_MASK) >> NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_SHIFT)
#define NDP120_CHIP_CONFIG_SPI_CFG_OVERRIDE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPI_CFG_DEFAULT 0x00000000U 
/* register ndp120.chip_config.dsp_cfg */
#define NDP120_CHIP_CONFIG_DSP_CFG 0x40009118U
#define NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_SHIFT 0
#define NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_MASK) >> NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_EN_DSP_CLK_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_SHIFT 1
#define NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_MASK) >> NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_RUN_STALL_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_DSP_CFG_BRESET_SHIFT 2
#define NDP120_CHIP_CONFIG_DSP_CFG_BRESET_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_DSP_CFG_BRESET(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_CFG_BRESET_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_BRESET_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_BRESET_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_BRESET_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_CFG_BRESET_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_BRESET_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_BRESET_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_CFG_BRESET_MASK) >> NDP120_CHIP_CONFIG_DSP_CFG_BRESET_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_BRESET_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_DSP_CFG_DRESET_SHIFT 3
#define NDP120_CHIP_CONFIG_DSP_CFG_DRESET_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_DSP_CFG_DRESET(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_CFG_DRESET_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_DRESET_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_DRESET_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_DRESET_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_CFG_DRESET_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_DRESET_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_DRESET_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_CFG_DRESET_MASK) >> NDP120_CHIP_CONFIG_DSP_CFG_DRESET_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_DRESET_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_SHIFT 4
#define NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_MASK 0x00000010U
#define NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_MASK) >> NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_STAT_VECTOR_SEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_SHIFT 5
#define NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_MASK 0x00000020U
#define NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_MASK) >> NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_CFG_OCD_HALT_ON_RESET_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_DSP_CFG_DEFAULT 0x0000000eU 
/* register ndp120.chip_config.dsp_status */
#define NDP120_CHIP_CONFIG_DSP_STATUS 0x4000911cU
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE_SHIFT 0
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE_MASK) >> NDP120_CHIP_CONFIG_DSP_STATUS_P_WAIT_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE_SHIFT 1
#define NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE_MASK) >> NDP120_CHIP_CONFIG_DSP_STATUS_IRAM0_LOAD_STORE_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE_SHIFT 2
#define NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE_MASK) >> NDP120_CHIP_CONFIG_DSP_STATUS_XOCD_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE_SHIFT 3
#define NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE_MASK) >> NDP120_CHIP_CONFIG_DSP_STATUS_DEBUG_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR_SHIFT 4
#define NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR_MASK 0x00000010U
#define NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR_MASK) >> NDP120_CHIP_CONFIG_DSP_STATUS_DOUBLE_EXCEPTION_ERROR_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR_SHIFT 5
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR_MASK 0x00000020U
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR_MASK) >> NDP120_CHIP_CONFIG_DSP_STATUS_P_FATAL_ERROR_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID_SHIFT 6
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID_MASK 0x00000040U
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID_MASK) >> NDP120_CHIP_CONFIG_DSP_STATUS_P_FAULT_INFO_VALID_SHIFT)
/* register ndp120.chip_config.dsp_fault_info */
#define NDP120_CHIP_CONFIG_DSP_FAULT_INFO 0x40009120U
#define NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO_SHIFT 0
#define NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO_MASK) >> NDP120_CHIP_CONFIG_DSP_FAULT_INFO_P_FAULT_INFO_SHIFT)
/* register ndp120.chip_config.dsp_mem_assist */
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST 0x40009124U
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_SHIFT 0
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_MASK 0x00000007U
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_MASK) >> NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_WRITE_ASSIST_DEFAULT 0x00000007U
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_SHIFT 3
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_MASK 0x00000038U
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_MASK) >> NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_READ_ASSIST_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_SHIFT 6
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_MASK 0x000000c0U
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_MASK) >> NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_WRITE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_SHIFT 8
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_MASK 0x00000700U
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_MASK) >> NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_MARGIN_READ_DEFAULT 0x00000007U
#define NDP120_CHIP_CONFIG_DSP_MEM_ASSIST_DEFAULT 0x00000707U 
/* register ndp120.chip_config.dsp_mem_pgen */
#define NDP120_CHIP_CONFIG_DSP_MEM_PGEN 0x40009128U
#define NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_SHIFT 0
#define NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_MASK 0x000000ffU
#define NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_MASK) >> NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DSP_PGEN_DEFAULT 0x000000ffU
#define NDP120_CHIP_CONFIG_DSP_MEM_PGEN_DEFAULT 0x000000ffU 
/* register ndp120.chip_config.dsp_mem_ret1n */
#define NDP120_CHIP_CONFIG_DSP_MEM_RET1N 0x4000912cU
#define NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_SHIFT 0
#define NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_MASK 0x000000ffU
#define NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_MASK) >> NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DSP_RET1N_DEFAULT 0x000000ffU
#define NDP120_CHIP_CONFIG_DSP_MEM_RET1N_DEFAULT 0x000000ffU 
/* register ndp120.chip_config.dsp_mem_ret2n */
#define NDP120_CHIP_CONFIG_DSP_MEM_RET2N 0x40009130U
#define NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_SHIFT 0
#define NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_MASK 0x000000ffU
#define NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N(v) \
        ((v) << NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_MASK) | ((v) << NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_SHIFT))
#define NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_MASK) >> NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_SHIFT)
#define NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DSP_RET2N_DEFAULT 0x000000ffU
#define NDP120_CHIP_CONFIG_DSP_MEM_RET2N_DEFAULT 0x000000ffU 
/* register ndp120.chip_config.dma_start_addr */
#define NDP120_CHIP_CONFIG_DMA_START_ADDR 0x40009134U
#define NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_SHIFT 0
#define NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR(v) \
        ((v) << NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_MASK) | ((v) << NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_MASK) >> NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_START_ADDR_START_ADDR_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_DMA_START_ADDR_DEFAULT 0x00000000U 
/* register ndp120.chip_config.dma_ctrl */
#define NDP120_CHIP_CONFIG_DMA_CTRL 0x40009138U
#define NDP120_CHIP_CONFIG_DMA_CTRL_START_SHIFT 0
#define NDP120_CHIP_CONFIG_DMA_CTRL_START_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_DMA_CTRL_START(v) \
        ((v) << NDP120_CHIP_CONFIG_DMA_CTRL_START_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_CTRL_START_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DMA_CTRL_START_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_CTRL_START_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DMA_CTRL_START_MASK) | ((v) << NDP120_CHIP_CONFIG_DMA_CTRL_START_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_CTRL_START_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DMA_CTRL_START_MASK) >> NDP120_CHIP_CONFIG_DMA_CTRL_START_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_CTRL_START_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_DMA_CTRL_STALL_SHIFT 1
#define NDP120_CHIP_CONFIG_DMA_CTRL_STALL_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_DMA_CTRL_STALL(v) \
        ((v) << NDP120_CHIP_CONFIG_DMA_CTRL_STALL_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_CTRL_STALL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DMA_CTRL_STALL_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_CTRL_STALL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DMA_CTRL_STALL_MASK) | ((v) << NDP120_CHIP_CONFIG_DMA_CTRL_STALL_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_CTRL_STALL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DMA_CTRL_STALL_MASK) >> NDP120_CHIP_CONFIG_DMA_CTRL_STALL_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_CTRL_STALL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_SHIFT 2
#define NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_DMA_CTRL_ABORT(v) \
        ((v) << NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_MASK) | ((v) << NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_MASK) >> NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_CTRL_ABORT_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_DMA_CTRL_DEFAULT 0x00000000U 
/* register ndp120.chip_config.dma_status */
#define NDP120_CHIP_CONFIG_DMA_STATUS 0x4000913cU
#define NDP120_CHIP_CONFIG_DMA_STATUS_DONE_SHIFT 0
#define NDP120_CHIP_CONFIG_DMA_STATUS_DONE_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_DMA_STATUS_DONE(v) \
        ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_STATUS_DONE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_STATUS_DONE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DMA_STATUS_DONE_MASK) | ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_STATUS_DONE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DMA_STATUS_DONE_MASK) >> NDP120_CHIP_CONFIG_DMA_STATUS_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_STATUS_BUSY_SHIFT 1
#define NDP120_CHIP_CONFIG_DMA_STATUS_BUSY_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_DMA_STATUS_BUSY(v) \
        ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_BUSY_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_STATUS_BUSY_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_BUSY_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_STATUS_BUSY_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DMA_STATUS_BUSY_MASK) | ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_BUSY_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_STATUS_BUSY_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DMA_STATUS_BUSY_MASK) >> NDP120_CHIP_CONFIG_DMA_STATUS_BUSY_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_STATUS_ERR_SHIFT 2
#define NDP120_CHIP_CONFIG_DMA_STATUS_ERR_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_DMA_STATUS_ERR(v) \
        ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_ERR_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_STATUS_ERR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_ERR_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_STATUS_ERR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DMA_STATUS_ERR_MASK) | ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_ERR_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_STATUS_ERR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DMA_STATUS_ERR_MASK) >> NDP120_CHIP_CONFIG_DMA_STATUS_ERR_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT_SHIFT 3
#define NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT_MASK 0x0007fff8U
#define NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT(v) \
        ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT_SHIFT)
#define NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT_MASK) | ((v) << NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT_SHIFT))
#define NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT_MASK) >> NDP120_CHIP_CONFIG_DMA_STATUS_REMAINING_CNT_SHIFT)
/* register ndp120.chip_config.multi_core_debug_cfg */
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG 0x40009140U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_SHIFT 0
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_RESET_DSP_BREAK_IN_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_SHIFT 1
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_IN_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_SHIFT 2
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_DSP_BREAK_OUT_ACK_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_SHIFT 3
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_STALLING_DSP_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_SHIFT 4
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_MASK 0x00000010U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_BREAKING_ARM_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_SHIFT 5
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_MASK 0x00000020U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_HALTED_STALLING_DSP_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_SHIFT 6
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_MASK 0x00000040U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_BREAKOUT_BREAKING_ARM_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_SHIFT 7
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_MASK 0x00000080U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_ENABLE_XOCD_MODE_RESTART_ARM_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_SHIFT 8
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_MASK 0x00000100U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_MCU_EDBGRQ_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_SHIFT 9
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_MASK 0x00000600U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_DISABLE 0x0U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_FOUR_WIRE 0x1U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_TWO_WIRE 0x2U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_REGISTER 0x3U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_MAX 0x3U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_MODE_VALID(v) \
        (v >= 0 && v <= 3)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_SHIFT 11
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_MASK 0x00001800U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_DRIVE2MA 0x0U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_DRIVE4MA 0x1U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_DRIVE6MA 0x2U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_DRIVE8MA 0x3U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_MAX 0x3U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_DRIVE_VALID(v) \
        (v >= 0 && v <= 3)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_SHIFT 13
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_MASK 0x00002000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_SMT_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_SHIFT 14
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_MASK 0x00004000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTAG_IDDQ_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_SHIFT 15
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_MASK 0x00008000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTMS_PU_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_SHIFT 16
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_MASK 0x00010000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTDI_PU_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_SHIFT 17
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_MASK 0x00020000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_SHIFT 18
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_MASK 0x00040000U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST(v) \
        ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_MASK) | ((v) << NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_SHIFT))
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_MASK) >> NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_SHIFT)
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_JTRST_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MULTI_CORE_DEBUG_CFG_DEFAULT 0x0005a0feU 
/* register ndp120.chip_config.cjtag_cfg */
#define NDP120_CHIP_CONFIG_CJTAG_CFG 0x40009144U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_SHIFT 0
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_MASK 0x00000007U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV(v) \
        ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_MASK) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_MASK) >> NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_INV_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_SHIFT 3
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_MASK) >> NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RST_ENABLE_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_SHIFT 4
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_MASK 0x00000010U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU(v) \
        ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_MASK) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_MASK) >> NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_PASSTHRU_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_SHIFT 5
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_MASK 0x00000060U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER(v) \
        ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_MASK) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_MASK) >> NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_NONE 0x0U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_KEEPER_TDO 0x1U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_MAX 0x1U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_KEEPER_VALID(v) \
        (v >= 0 && v <= 1)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_SHIFT 7
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_MASK 0x0007ff80U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC(v) \
        ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_MASK) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_MASK) >> NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_OAC_DEFAULT 0x00000310U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_SHIFT 19
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_MASK 0x00080000U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB(v) \
        ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_MASK) | ((v) << NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_MASK) >> NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_CJTAG_CFG_CJTAG_RSTB_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_CJTAG_CFG_DEFAULT 0x00098829U 
/* register ndp120.chip_config.jtag_cmd */
#define NDP120_CHIP_CONFIG_JTAG_CMD 0x40009148U
#define NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_SHIFT 0
#define NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_MASK) >> NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_SHIFT 1
#define NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_MASK 0x0000000eU
#define NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS(v) \
        ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_MASK) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_MASK) >> NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_NUM_BITS_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_SHIFT 4
#define NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_MASK 0x00000010U
#define NDP120_CHIP_CONFIG_JTAG_CMD_DIV64(v) \
        ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_MASK) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_MASK) >> NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_DIV32 0x0U
#define NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_DIV64 0x1U
#define NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_MAX 0x1U
#define NDP120_CHIP_CONFIG_JTAG_CMD_DIV64_VALID(v) \
        (v >= 0 && v <= 1)
#define NDP120_CHIP_CONFIG_JTAG_CMD_DONE_SHIFT 5
#define NDP120_CHIP_CONFIG_JTAG_CMD_DONE_MASK 0x00000020U
#define NDP120_CHIP_CONFIG_JTAG_CMD_DONE(v) \
        ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_DONE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_DONE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_JTAG_CMD_DONE_MASK) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_DONE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_JTAG_CMD_DONE_MASK) >> NDP120_CHIP_CONFIG_JTAG_CMD_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_SHIFT 8
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_MASK 0x0000ff00U
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTMS(v) \
        ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_MASK) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_MASK) >> NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTMS_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_SHIFT 16
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_MASK 0x00ff0000U
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDI(v) \
        ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_MASK) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_MASK) >> NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDI_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDO_SHIFT 24
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDO_MASK 0xff000000U
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDO(v) \
        ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_JTDO_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDO_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_JTDO_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDO_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_JTAG_CMD_JTDO_MASK) | ((v) << NDP120_CHIP_CONFIG_JTAG_CMD_JTDO_SHIFT))
#define NDP120_CHIP_CONFIG_JTAG_CMD_JTDO_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_JTAG_CMD_JTDO_MASK) >> NDP120_CHIP_CONFIG_JTAG_CMD_JTDO_SHIFT)
#define NDP120_CHIP_CONFIG_JTAG_CMD_DEFAULT 0x00000000U 
/* register ndp120.chip_config.vidcfg0 */
#define NDP120_CHIP_CONFIG_VIDCFG0 0x4000914cU
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_SHIFT 0
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_MASK) >> NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_VIDCFG0_RSTB_SHIFT 1
#define NDP120_CHIP_CONFIG_VIDCFG0_RSTB_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_VIDCFG0_RSTB(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG0_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_RSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_RSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG0_RSTB_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_RSTB_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_RSTB_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG0_RSTB_MASK) >> NDP120_CHIP_CONFIG_VIDCFG0_RSTB_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_RSTB_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_SHIFT 2
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_MASK) >> NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_ENABLE_INTERFACE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_SHIFT 3
#define NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_MASK) >> NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_ACTIVE_LOW_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_SHIFT 4
#define NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_MASK 0x00000010U
#define NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_MASK) >> NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_VSYNC_PULSE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_SHIFT 5
#define NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_MASK 0x00000020U
#define NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_MASK) >> NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_BIG_ENDIAN_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_SHIFT 6
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_MASK 0x000000c0U
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_MASK) >> NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_DEFAULT 0x00000002U
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_BIT_1 0x0U
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_BIT_4 0x1U
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_BIT_8 0x2U
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_MAX 0x2U
#define NDP120_CHIP_CONFIG_VIDCFG0_NUM_BITS_VALID(v) \
        (v >= 0 && v <= 2)
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_SHIFT 8
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_MASK 0x00000300U
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_MASK) >> NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_BURST_1 0x0U
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_BURST_4 0x1U
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_BURST_8 0x2U
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_MAX 0x2U
#define NDP120_CHIP_CONFIG_VIDCFG0_MAX_BURST_VALID(v) \
        (v >= 0 && v <= 2)
#define NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_SHIFT(i) (((i) * 10) + 10)
#define NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_MASK(i) \
        (0x3ffU << NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE(i, v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_INSERT(x, i, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_SHIFT(i)))
#define NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_MASK_INSERT(x, i, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_MASK(i)) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_SHIFT(i)))
#define NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_EXTRACT(x, i) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_MASK(i)) >> NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_COUNT 2
#define NDP120_CHIP_CONFIG_VIDCFG0_FRAME_SIZE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_SHIFT 30
#define NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_MASK 0x40000000U
#define NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_MASK) >> NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG0_INT_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_VIDCFG0_DEFAULT 0x000001a2U 
/* register ndp120.chip_config.vidcfg1 */
#define NDP120_CHIP_CONFIG_VIDCFG1 0x40009150U
#define NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_SHIFT(i) (((i) * 10) + 0)
#define NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_MASK(i) \
        (0x3ffU << NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE(i, v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_INSERT(x, i, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_SHIFT(i)))
#define NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_MASK_INSERT(x, i, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_MASK(i)) | ((v) << NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_SHIFT(i)))
#define NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_EXTRACT(x, i) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_MASK(i)) >> NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_COUNT 2
#define NDP120_CHIP_CONFIG_VIDCFG1_IMAGE_SIZE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_SHIFT 20
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_MASK 0x00100000U
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_MASK) >> NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_VID_CLK_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_SHIFT 21
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_MASK 0x00200000U
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_SHIFT))
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_MASK) >> NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_SHIFT)
#define NDP120_CHIP_CONFIG_VIDCFG1_FORCE_DISABLE_VSYNC_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_VIDCFG1_DEFAULT 0x00000000U 
/* register ndp120.chip_config.vidcfg2 */
#define NDP120_CHIP_CONFIG_VIDCFG2 0x40009154U
#define NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_SHIFT(i) (((i) * 10) + 0)
#define NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_MASK(i) \
        (0x3ffU << NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC(i, v) \
        ((v) << NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_INSERT(x, i, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_SHIFT(i)))
#define NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_MASK_INSERT(x, i, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_MASK(i)) | ((v) << NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_SHIFT(i)))
#define NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_EXTRACT(x, i) \
        (((x) & NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_MASK(i)) >> NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_COUNT 2
#define NDP120_CHIP_CONFIG_VIDCFG2_IMAGE_LOC_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_VIDCFG2_DEFAULT 0x00000000U 
/* register array ndp120.chip_config.vidaddr[2] */
#define NDP120_CHIP_CONFIG_VIDADDR(i) (0x40009158U + ((i) << 2))
#define NDP120_CHIP_CONFIG_VIDADDR_COUNT 2
#define NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_SHIFT 0
#define NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_MASK) >> NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_VIDADDR_BASE_ADDR_DEFAULT 0x60000000U
#define NDP120_CHIP_CONFIG_VIDADDR_DEFAULT 0x60000000U 
/* register ndp120.chip_config.vidsts0 */
#define NDP120_CHIP_CONFIG_VIDSTS0 0x40009160U
#define NDP120_CHIP_CONFIG_VIDSTS0_EOF_SHIFT 0
#define NDP120_CHIP_CONFIG_VIDSTS0_EOF_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_VIDSTS0_EOF(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDSTS0_EOF_SHIFT)
#define NDP120_CHIP_CONFIG_VIDSTS0_EOF_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDSTS0_EOF_SHIFT))
#define NDP120_CHIP_CONFIG_VIDSTS0_EOF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDSTS0_EOF_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDSTS0_EOF_SHIFT))
#define NDP120_CHIP_CONFIG_VIDSTS0_EOF_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDSTS0_EOF_MASK) >> NDP120_CHIP_CONFIG_VIDSTS0_EOF_SHIFT)
#define NDP120_CHIP_CONFIG_VIDSTS0_RUNNING_SHIFT 1
#define NDP120_CHIP_CONFIG_VIDSTS0_RUNNING_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_VIDSTS0_RUNNING(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDSTS0_RUNNING_SHIFT)
#define NDP120_CHIP_CONFIG_VIDSTS0_RUNNING_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDSTS0_RUNNING_SHIFT))
#define NDP120_CHIP_CONFIG_VIDSTS0_RUNNING_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDSTS0_RUNNING_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDSTS0_RUNNING_SHIFT))
#define NDP120_CHIP_CONFIG_VIDSTS0_RUNNING_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDSTS0_RUNNING_MASK) >> NDP120_CHIP_CONFIG_VIDSTS0_RUNNING_SHIFT)
#define NDP120_CHIP_CONFIG_VIDSTS0_ERROR_SHIFT 2
#define NDP120_CHIP_CONFIG_VIDSTS0_ERROR_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_VIDSTS0_ERROR(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDSTS0_ERROR_SHIFT)
#define NDP120_CHIP_CONFIG_VIDSTS0_ERROR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDSTS0_ERROR_SHIFT))
#define NDP120_CHIP_CONFIG_VIDSTS0_ERROR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDSTS0_ERROR_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDSTS0_ERROR_SHIFT))
#define NDP120_CHIP_CONFIG_VIDSTS0_ERROR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDSTS0_ERROR_MASK) >> NDP120_CHIP_CONFIG_VIDSTS0_ERROR_SHIFT)
#define NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX_SHIFT 3
#define NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX_MASK 0x00001ff8U
#define NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX_SHIFT)
#define NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX_SHIFT))
#define NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX_SHIFT))
#define NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX_MASK) >> NDP120_CHIP_CONFIG_VIDSTS0_FRAME_INDEX_SHIFT)
/* register ndp120.chip_config.vidsts1 */
#define NDP120_CHIP_CONFIG_VIDSTS1 0x40009164U
#define NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_SHIFT(i) (((i) * 10) + 0)
#define NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_MASK(i) \
        (0x3ffU << NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE(i, v) \
        ((v) << NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_INSERT(x, i, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_SHIFT(i)))
#define NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_MASK_INSERT(x, i, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_MASK(i)) | ((v) << NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_SHIFT(i)))
#define NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_EXTRACT(x, i) \
        (((x) & NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_MASK(i)) >> NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_SHIFT(i))
#define NDP120_CHIP_CONFIG_VIDSTS1_FRAME_SIZE_COUNT 2
/* register ndp120.chip_config.vidsts2 */
#define NDP120_CHIP_CONFIG_VIDSTS2 0x40009168U
#define NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT_SHIFT 0
#define NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT_MASK 0x000fffffU
#define NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT(v) \
        ((v) << NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT_SHIFT)
#define NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT_SHIFT))
#define NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT_MASK) | ((v) << NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT_SHIFT))
#define NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT_MASK) >> NDP120_CHIP_CONFIG_VIDSTS2_BYTE_COUNT_SHIFT)
/* register ndp120.chip_config.hostspiaddr */
#define NDP120_CHIP_CONFIG_HOSTSPIADDR 0x4000916cU
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_SHIFT 0
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_MASK 0x0000001fU
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR(v) \
        ((v) << NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_MASK) | ((v) << NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_MASK) >> NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_READ_ADDR_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_SHIFT 5
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_MASK 0x00000020U
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE(v) \
        ((v) << NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_MASK) | ((v) << NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_MASK) >> NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_ENABLE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_SHIFT 6
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_MASK 0x00003fc0U
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK(v) \
        ((v) << NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_MASK) | ((v) << NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_SHIFT))
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_MASK) >> NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_SHIFT)
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_INT_MASK_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_HOSTSPIADDR_DEFAULT 0x00000000U 
/* register ndp120.chip_config.hostspidata */
#define NDP120_CHIP_CONFIG_HOSTSPIDATA 0x40009170U
/* register array ndp120.chip_config.spare[2] */
#define NDP120_CHIP_CONFIG_SPARE(i) (0x40009174U + ((i) << 2))
#define NDP120_CHIP_CONFIG_SPARE_COUNT 2
#define NDP120_CHIP_CONFIG_SPARE_WORD_SHIFT 0
#define NDP120_CHIP_CONFIG_SPARE_WORD_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_SPARE_WORD(v) \
        ((v) << NDP120_CHIP_CONFIG_SPARE_WORD_SHIFT)
#define NDP120_CHIP_CONFIG_SPARE_WORD_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_SPARE_WORD_SHIFT))
#define NDP120_CHIP_CONFIG_SPARE_WORD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_SPARE_WORD_MASK) | ((v) << NDP120_CHIP_CONFIG_SPARE_WORD_SHIFT))
#define NDP120_CHIP_CONFIG_SPARE_WORD_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_SPARE_WORD_MASK) >> NDP120_CHIP_CONFIG_SPARE_WORD_SHIFT)
#define NDP120_CHIP_CONFIG_SPARE_WORD_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_SPARE_DEFAULT 0x00000000U 
/* register ndp120.chip_config.qspikey */
#define NDP120_CHIP_CONFIG_QSPIKEY 0x4000917cU
#define NDP120_CHIP_CONFIG_QSPIKEY_KEY_SHIFT 0
#define NDP120_CHIP_CONFIG_QSPIKEY_KEY_MASK 0x000000ffU
#define NDP120_CHIP_CONFIG_QSPIKEY_KEY(v) \
        ((v) << NDP120_CHIP_CONFIG_QSPIKEY_KEY_SHIFT)
#define NDP120_CHIP_CONFIG_QSPIKEY_KEY_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_QSPIKEY_KEY_SHIFT))
#define NDP120_CHIP_CONFIG_QSPIKEY_KEY_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_QSPIKEY_KEY_MASK) | ((v) << NDP120_CHIP_CONFIG_QSPIKEY_KEY_SHIFT))
#define NDP120_CHIP_CONFIG_QSPIKEY_KEY_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_QSPIKEY_KEY_MASK) >> NDP120_CHIP_CONFIG_QSPIKEY_KEY_SHIFT)
#define NDP120_CHIP_CONFIG_QSPIKEY_KEY_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_QSPIKEY_KEY_DISABLE 0x0U
#define NDP120_CHIP_CONFIG_QSPIKEY_KEY_ENABLE 0x3dU
#define NDP120_CHIP_CONFIG_QSPIKEY_KEY_MAX 0x3dU
#define NDP120_CHIP_CONFIG_QSPIKEY_KEY_VALID(v) \
        (v == NDP120_CHIP_CONFIG_QSPIKEY_KEY_DISABLE || v == NDP120_CHIP_CONFIG_QSPIKEY_KEY_ENABLE)
#define NDP120_CHIP_CONFIG_QSPIKEY_DEFAULT 0x00000000U 
/* register ndp120.chip_config.test_control */
#define NDP120_CHIP_CONFIG_TEST_CONTROL 0x40009180U
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_SHIFT 0
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_MASK 0x0000001fU
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0(v) \
        ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_SHIFT)
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_SHIFT))
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_MASK) | ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_SHIFT))
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_MASK) >> NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_SHIFT)
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL0_DEFAULT 0x0000001fU
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_SHIFT 5
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_MASK 0x000003e0U
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1(v) \
        ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_SHIFT)
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_SHIFT))
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_MASK) | ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_SHIFT))
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_MASK) >> NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_SHIFT)
#define NDP120_CHIP_CONFIG_TEST_CONTROL_CLK_SEL1_DEFAULT 0x0000001fU
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_SHIFT 10
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_MASK 0x00007c00U
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_MASK) >> NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_DONE_SEL_DEFAULT 0x0000001fU
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_SHIFT 15
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_MASK 0x000f8000U
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_MASK) >> NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_TEST_CONTROL_MBIST_FAIL_SEL_DEFAULT 0x0000001fU
#define NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_SHIFT 20
#define NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_MASK 0x01f00000U
#define NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_MASK) >> NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_TEST_CONTROL_LOCK_SEL_DEFAULT 0x0000001fU
#define NDP120_CHIP_CONFIG_TEST_CONTROL_DEFAULT 0x01ffffffU 
/* register ndp120.chip_config.mbist_host_cmd */
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD 0x40009184U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_MASK 0x0000003fU
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_ALL 0x20U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_MAX 0x20U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_SLEEP || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_ALGO_SEL_ALL)
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_SHIFT 6
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_MASK 0x000fffc0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_BOOTROM 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_RAM 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DSP_DRAM 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DSP_IRAM 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNDATA0_0 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNDATA0_1 0x20U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNDATA1_0 0x40U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNDATA1_1 0x80U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNPARAMS_0 0x100U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNPARAMS_1 0x200U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNPARAMS_2 0x400U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNPARAMS_3 0x800U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNPARAMS_4 0x1000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_REGFILE 0x2000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_MAX 0x2000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_BOOTROM || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_RAM || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DSP_DRAM || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DSP_IRAM || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNDATA0_0 || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNDATA0_1 || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNDATA1_0 || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNDATA1_1 || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNPARAMS_0 || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNPARAMS_1 || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNPARAMS_2 || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNPARAMS_3 || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_DNNPARAMS_4 || v == NDP120_CHIP_CONFIG_MBIST_HOST_CMD_MEM_SEL_REGFILE)
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_SHIFT 20
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_MASK 0x00100000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_START_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_SHIFT 21
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_MASK 0x00200000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_RESUME_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_CMD_DEFAULT 0x00000000U 
/* register ndp120.chip_config.mbist_host_resp_all */
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL 0x40009188U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL_SHIFT 1
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_ALL_TEST_FAIL_SHIFT)
/* register ndp120.chip_config.mbist_host_resp_0 */
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0 0x4000918cU
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_MASK 0x0000001fU
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_BOOTRAM_SLEEP)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_SHIFT 5
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_MASK 0x000003e0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_RAM_SLEEP)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_SHIFT 10
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_MASK 0x00007c00U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_DRAM_SLEEP)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_SHIFT 15
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_MASK 0x000f8000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_0_TEST_FAIL_DSP_IRAM_SLEEP)
/* register ndp120.chip_config.mbist_host_resp_1 */
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1 0x40009190U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_MASK 0x0000001fU
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_0_SLEEP)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_SHIFT 5
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_MASK 0x000003e0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA0_1_SLEEP)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_SHIFT 10
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_MASK 0x00007c00U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_0_SLEEP)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_SHIFT 15
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_MASK 0x000f8000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_1_TEST_FAIL_DNNDATA1_1_SLEEP)
/* register ndp120.chip_config.mbist_host_resp_2 */
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2 0x40009194U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_MASK 0x0000001fU
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_0_SLEEP)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_SHIFT 5
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_MASK 0x000003e0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_1_SLEEP)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_SHIFT 10
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_MASK 0x00007c00U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_2_SLEEP)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_SHIFT 15
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_MASK 0x000f8000U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_2_TEST_FAIL_DNNPARAMS_3_SLEEP)
/* register ndp120.chip_config.mbist_host_resp_3 */
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3 0x40009198U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_MASK 0x0000001fU
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_DNNPARAMS_4_SLEEP)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_SHIFT 5
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_MASK 0x000003e0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_MASK) >> NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_MAX 0x10U
#define NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_NONE || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_SCAN || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_HOST_RESP_3_TEST_FAIL_REGFILE_SLEEP)
/* register ndp120.chip_config.mbist_cfg_0 */
#define NDP120_CHIP_CONFIG_MBIST_CFG_0 0x4000919cU
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_OVRD_START_END_ADDR_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_SHIFT 1
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_MASK 0x00003ffeU
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_START_ADDR_OVRD_VAL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_SHIFT 14
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_MASK 0x0fffc000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_NUM_WORDS_OVRD_VAL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_0_DEFAULT 0x00000000U 
/* register ndp120.chip_config.mbist_cfg_1 */
#define NDP120_CHIP_CONFIG_MBIST_CFG_1 0x400091a0U
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_MASK 0x00003fffU
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_T_RAM_SEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_SHIFT 14
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_MASK 0x0003c000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_WIDTH_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_SHIFT 18
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_MASK 0xfffc0000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_MEM_DESC_OVRD_VAL_NUM_WORDS_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_1_DEFAULT 0x00000000U 
/* register ndp120.chip_config.mbist_cfg_2 */
#define NDP120_CHIP_CONFIG_MBIST_CFG_2 0x400091a4U
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_MEM_DESC_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_SHIFT 1
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_OVRD_T_RAM_SEL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_SHIFT 2
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_MASK 0x0000fffcU
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_T_RAM_SEL_OVRD_VAL_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_2_DEFAULT 0x00000000U 
/* register ndp120.chip_config.mbist_cfg_3 */
#define NDP120_CHIP_CONFIG_MBIST_CFG_3 0x400091a8U
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_MASK 0x00000001U
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_MBIST_CLK_EN_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_SHIFT 1
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_MASK 0x00000002U
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_STOP_TEST_ON_ERROR_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_SHIFT 2
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_MASK 0x00000004U
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_RESET_MBIST_ENGINE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_SHIFT 3
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_MASK 0x00000008U
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_PAUSE_ON_ERROR_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_SHIFT 4
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_MASK 0x00fffff0U
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_MASK) >> NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_LF_CHECK_WAIT_PERIOD_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MBIST_CFG_3_DEFAULT 0x00000000U 
/* register ndp120.chip_config.mbist_diag_0 */
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0 0x400091acU
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_MASK 0x0000003fU
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_MASK) >> NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_CONNECTIVITY 0x1U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_SCAN 0x2U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_MARCHSR 0x4U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_BLIFPLUS 0x8U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_SLEEP 0x10U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_ALL 0x20U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_MAX 0x20U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_NONE || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_CONNECTIVITY || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_SCAN || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_MARCHSR || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_BLIFPLUS || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_SLEEP || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_ALGO_SEL_ALL)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_SHIFT 6
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_MASK 0x000fffc0U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_MASK) >> NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_NONE 0x0U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_BOOTROM 0x1U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_RAM 0x2U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DSP_DRAM 0x4U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DSP_IRAM 0x8U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNDATA0_0 0x10U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNDATA0_1 0x20U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNDATA1_0 0x40U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNDATA1_1 0x80U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNPARAMS_0 0x100U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNPARAMS_1 0x200U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNPARAMS_2 0x400U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNPARAMS_3 0x800U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNPARAMS_4 0x1000U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_REGFILE 0x2000U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_MAX 0x2000U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_VALID(v) \
        (v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_NONE || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_BOOTROM || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_RAM || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DSP_DRAM || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DSP_IRAM || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNDATA0_0 || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNDATA0_1 || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNDATA1_0 || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNDATA1_1 || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNPARAMS_0 || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNPARAMS_1 || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNPARAMS_2 || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNPARAMS_3 || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_DNNPARAMS_4 || v == NDP120_CHIP_CONFIG_MBIST_DIAG_0_MEM_SEL_REGFILE)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG_SHIFT 20
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG_MASK 0x00300000U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG_MASK) >> NDP120_CHIP_CONFIG_MBIST_DIAG_0_DATA_BG_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER_SHIFT 22
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER_MASK 0x00400000U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER_MASK) >> NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_ORDER_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE_SHIFT 23
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE_MASK 0x00800000U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE_MASK) >> NDP120_CHIP_CONFIG_MBIST_DIAG_0_ADDR_UPDATE_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL_SHIFT 24
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL_MASK 0x07000000U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL_MASK) >> NDP120_CHIP_CONFIG_MBIST_DIAG_0_OP_SEL_SHIFT)
/* register ndp120.chip_config.mbist_diag_1 */
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1 0x400091b0U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR_SHIFT 0
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR_MASK 0x00001fffU
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR_MASK) >> NDP120_CHIP_CONFIG_MBIST_DIAG_1_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA_SHIFT 13
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA_MASK 0x00002000U
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA(v) \
        ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA_SHIFT)
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA_MASK) | ((v) << NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA_SHIFT))
#define NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA_MASK) >> NDP120_CHIP_CONFIG_MBIST_DIAG_1_DATA_SHIFT)
/* register ndp120.chip_config.mcu_spi_access_cfg */
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG 0x400091b4U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_SHIFT 0
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_MASK 0x00000003U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE(v) \
        ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_MASK) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_MASK) >> NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_IDLE 0x0U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_TRANSFER 0x1U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_UPDATE 0x2U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_MAX 0x2U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_MODE_VALID(v) \
        (v >= 0 && v <= 2)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_SHIFT 2
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_MASK 0x000001fcU
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR(v) \
        ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_MASK) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_MASK) >> NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_ADDR_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_SHIFT 9
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_MASK 0x00000200U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN(v) \
        ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_MASK) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_MASK) >> NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_RWN_DEFAULT 0x00000001U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_SHIFT 10
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_MASK 0x00000c00U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES(v) \
        ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_MASK) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_MASK) >> NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_NUM_BYTES_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE_SHIFT 12
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE_MASK 0x00001000U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE(v) \
        ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE_MASK) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE_MASK) >> NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DONE_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_CFG_DEFAULT 0x00000200U 
/* register ndp120.chip_config.mcu_spi_access_wdata */
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA 0x400091b8U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_SHIFT 0
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA(v) \
        ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_MASK) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_MASK) >> NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_WDATA_DEFAULT 0x00000000U
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_WDATA_DEFAULT 0x00000000U 
/* register ndp120.chip_config.mcu_spi_access_rdata */
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA 0x400091bcU
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA_SHIFT 0
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA_MASK 0xffffffffU
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA(v) \
        ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA_SHIFT)
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA_INSERT(x, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA_MASK) | ((v) << NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA_SHIFT))
#define NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA_EXTRACT(x) \
        (((x) & NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA_MASK) >> NDP120_CHIP_CONFIG_MCU_SPI_ACCESS_RDATA_RDATA_SHIFT)
/* register array ndp120.chip_config.gpio_intr_sel[2] */
#define NDP120_CHIP_CONFIG_GPIO_INTR_SEL(i) (0x400091c0U + ((i) << 2))
#define NDP120_CHIP_CONFIG_GPIO_INTR_SEL_COUNT 2
#define NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_SHIFT(i) (((i) * 6) + 0)
#define NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_MASK(i) \
        (0x3fU << NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_SHIFT(i))
#define NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL(i, v) \
        ((v) << NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_SHIFT(i))
#define NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_INSERT(x, i, v) \
        ((x) | ((v) << NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_SHIFT(i)))
#define NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_MASK_INSERT(x, i, v) \
        (((x) & ~NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_MASK(i)) | ((v) << NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_SHIFT(i)))
#define NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_EXTRACT(x, i) \
        (((x) & NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_MASK(i)) >> NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_SHIFT(i))
#define NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_COUNT 4
#define NDP120_CHIP_CONFIG_GPIO_INTR_SEL_INTR_SEL_DEFAULT 0x00000020U
#define NDP120_CHIP_CONFIG_GPIO_INTR_SEL_DEFAULT 0x00000020U 

/*
 * block ndp120.i2c_config, base 0x4000a000
 */
#define NDP120_I2C_CONFIG 0x4000a000U
#define NDP120_I2C_CONFIG_SIZE 0x00001000U
/* register ndp120.i2c_config.cr */
#define NDP120_I2C_CONFIG_CR 0x4000a000U
#define NDP120_I2C_CONFIG_CR_RW_SHIFT 0
#define NDP120_I2C_CONFIG_CR_RW_MASK 0x00000001U
#define NDP120_I2C_CONFIG_CR_RW(v) \
        ((v) << NDP120_I2C_CONFIG_CR_RW_SHIFT)
#define NDP120_I2C_CONFIG_CR_RW_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_CR_RW_SHIFT))
#define NDP120_I2C_CONFIG_CR_RW_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_CR_RW_MASK) | ((v) << NDP120_I2C_CONFIG_CR_RW_SHIFT))
#define NDP120_I2C_CONFIG_CR_RW_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_CR_RW_MASK) >> NDP120_I2C_CONFIG_CR_RW_SHIFT)
#define NDP120_I2C_CONFIG_CR_RW_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_CR_MS_SHIFT 1
#define NDP120_I2C_CONFIG_CR_MS_MASK 0x00000002U
#define NDP120_I2C_CONFIG_CR_MS(v) \
        ((v) << NDP120_I2C_CONFIG_CR_MS_SHIFT)
#define NDP120_I2C_CONFIG_CR_MS_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_CR_MS_SHIFT))
#define NDP120_I2C_CONFIG_CR_MS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_CR_MS_MASK) | ((v) << NDP120_I2C_CONFIG_CR_MS_SHIFT))
#define NDP120_I2C_CONFIG_CR_MS_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_CR_MS_MASK) >> NDP120_I2C_CONFIG_CR_MS_SHIFT)
#define NDP120_I2C_CONFIG_CR_MS_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_CR_NEA_SHIFT 2
#define NDP120_I2C_CONFIG_CR_NEA_MASK 0x00000004U
#define NDP120_I2C_CONFIG_CR_NEA(v) \
        ((v) << NDP120_I2C_CONFIG_CR_NEA_SHIFT)
#define NDP120_I2C_CONFIG_CR_NEA_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_CR_NEA_SHIFT))
#define NDP120_I2C_CONFIG_CR_NEA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_CR_NEA_MASK) | ((v) << NDP120_I2C_CONFIG_CR_NEA_SHIFT))
#define NDP120_I2C_CONFIG_CR_NEA_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_CR_NEA_MASK) >> NDP120_I2C_CONFIG_CR_NEA_SHIFT)
#define NDP120_I2C_CONFIG_CR_NEA_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_CR_ACKEN_SHIFT 3
#define NDP120_I2C_CONFIG_CR_ACKEN_MASK 0x00000008U
#define NDP120_I2C_CONFIG_CR_ACKEN(v) \
        ((v) << NDP120_I2C_CONFIG_CR_ACKEN_SHIFT)
#define NDP120_I2C_CONFIG_CR_ACKEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_CR_ACKEN_SHIFT))
#define NDP120_I2C_CONFIG_CR_ACKEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_CR_ACKEN_MASK) | ((v) << NDP120_I2C_CONFIG_CR_ACKEN_SHIFT))
#define NDP120_I2C_CONFIG_CR_ACKEN_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_CR_ACKEN_MASK) >> NDP120_I2C_CONFIG_CR_ACKEN_SHIFT)
#define NDP120_I2C_CONFIG_CR_ACKEN_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_CR_HOLD_SHIFT 4
#define NDP120_I2C_CONFIG_CR_HOLD_MASK 0x00000010U
#define NDP120_I2C_CONFIG_CR_HOLD(v) \
        ((v) << NDP120_I2C_CONFIG_CR_HOLD_SHIFT)
#define NDP120_I2C_CONFIG_CR_HOLD_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_CR_HOLD_SHIFT))
#define NDP120_I2C_CONFIG_CR_HOLD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_CR_HOLD_MASK) | ((v) << NDP120_I2C_CONFIG_CR_HOLD_SHIFT))
#define NDP120_I2C_CONFIG_CR_HOLD_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_CR_HOLD_MASK) >> NDP120_I2C_CONFIG_CR_HOLD_SHIFT)
#define NDP120_I2C_CONFIG_CR_HOLD_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_CR_SLVMON_SHIFT 5
#define NDP120_I2C_CONFIG_CR_SLVMON_MASK 0x00000020U
#define NDP120_I2C_CONFIG_CR_SLVMON(v) \
        ((v) << NDP120_I2C_CONFIG_CR_SLVMON_SHIFT)
#define NDP120_I2C_CONFIG_CR_SLVMON_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_CR_SLVMON_SHIFT))
#define NDP120_I2C_CONFIG_CR_SLVMON_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_CR_SLVMON_MASK) | ((v) << NDP120_I2C_CONFIG_CR_SLVMON_SHIFT))
#define NDP120_I2C_CONFIG_CR_SLVMON_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_CR_SLVMON_MASK) >> NDP120_I2C_CONFIG_CR_SLVMON_SHIFT)
#define NDP120_I2C_CONFIG_CR_SLVMON_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_CR_CLRFIFO_SHIFT 6
#define NDP120_I2C_CONFIG_CR_CLRFIFO_MASK 0x00000040U
#define NDP120_I2C_CONFIG_CR_CLRFIFO(v) \
        ((v) << NDP120_I2C_CONFIG_CR_CLRFIFO_SHIFT)
#define NDP120_I2C_CONFIG_CR_CLRFIFO_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_CR_CLRFIFO_SHIFT))
#define NDP120_I2C_CONFIG_CR_CLRFIFO_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_CR_CLRFIFO_MASK) | ((v) << NDP120_I2C_CONFIG_CR_CLRFIFO_SHIFT))
#define NDP120_I2C_CONFIG_CR_CLRFIFO_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_CR_CLRFIFO_MASK) >> NDP120_I2C_CONFIG_CR_CLRFIFO_SHIFT)
#define NDP120_I2C_CONFIG_CR_CLRFIFO_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_CR_DIV_A_SHIFT 8
#define NDP120_I2C_CONFIG_CR_DIV_A_MASK 0x00003f00U
#define NDP120_I2C_CONFIG_CR_DIV_A(v) \
        ((v) << NDP120_I2C_CONFIG_CR_DIV_A_SHIFT)
#define NDP120_I2C_CONFIG_CR_DIV_A_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_CR_DIV_A_SHIFT))
#define NDP120_I2C_CONFIG_CR_DIV_A_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_CR_DIV_A_MASK) | ((v) << NDP120_I2C_CONFIG_CR_DIV_A_SHIFT))
#define NDP120_I2C_CONFIG_CR_DIV_A_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_CR_DIV_A_MASK) >> NDP120_I2C_CONFIG_CR_DIV_A_SHIFT)
#define NDP120_I2C_CONFIG_CR_DIV_A_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_CR_DIV_B_SHIFT 14
#define NDP120_I2C_CONFIG_CR_DIV_B_MASK 0x0000c000U
#define NDP120_I2C_CONFIG_CR_DIV_B(v) \
        ((v) << NDP120_I2C_CONFIG_CR_DIV_B_SHIFT)
#define NDP120_I2C_CONFIG_CR_DIV_B_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_CR_DIV_B_SHIFT))
#define NDP120_I2C_CONFIG_CR_DIV_B_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_CR_DIV_B_MASK) | ((v) << NDP120_I2C_CONFIG_CR_DIV_B_SHIFT))
#define NDP120_I2C_CONFIG_CR_DIV_B_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_CR_DIV_B_MASK) >> NDP120_I2C_CONFIG_CR_DIV_B_SHIFT)
#define NDP120_I2C_CONFIG_CR_DIV_B_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_CR_DEFAULT 0x00000000U 
/* register ndp120.i2c_config.sr */
#define NDP120_I2C_CONFIG_SR 0x4000a004U
#define NDP120_I2C_CONFIG_SR_RXRW_SHIFT 3
#define NDP120_I2C_CONFIG_SR_RXRW_MASK 0x00000008U
#define NDP120_I2C_CONFIG_SR_RXRW(v) \
        ((v) << NDP120_I2C_CONFIG_SR_RXRW_SHIFT)
#define NDP120_I2C_CONFIG_SR_RXRW_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_SR_RXRW_SHIFT))
#define NDP120_I2C_CONFIG_SR_RXRW_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_SR_RXRW_MASK) | ((v) << NDP120_I2C_CONFIG_SR_RXRW_SHIFT))
#define NDP120_I2C_CONFIG_SR_RXRW_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_SR_RXRW_MASK) >> NDP120_I2C_CONFIG_SR_RXRW_SHIFT)
#define NDP120_I2C_CONFIG_SR_RXRW_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_SR_RXDV_SHIFT 5
#define NDP120_I2C_CONFIG_SR_RXDV_MASK 0x00000020U
#define NDP120_I2C_CONFIG_SR_RXDV(v) \
        ((v) << NDP120_I2C_CONFIG_SR_RXDV_SHIFT)
#define NDP120_I2C_CONFIG_SR_RXDV_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_SR_RXDV_SHIFT))
#define NDP120_I2C_CONFIG_SR_RXDV_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_SR_RXDV_MASK) | ((v) << NDP120_I2C_CONFIG_SR_RXDV_SHIFT))
#define NDP120_I2C_CONFIG_SR_RXDV_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_SR_RXDV_MASK) >> NDP120_I2C_CONFIG_SR_RXDV_SHIFT)
#define NDP120_I2C_CONFIG_SR_RXDV_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_SR_TXDV_SHIFT 6
#define NDP120_I2C_CONFIG_SR_TXDV_MASK 0x00000040U
#define NDP120_I2C_CONFIG_SR_TXDV(v) \
        ((v) << NDP120_I2C_CONFIG_SR_TXDV_SHIFT)
#define NDP120_I2C_CONFIG_SR_TXDV_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_SR_TXDV_SHIFT))
#define NDP120_I2C_CONFIG_SR_TXDV_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_SR_TXDV_MASK) | ((v) << NDP120_I2C_CONFIG_SR_TXDV_SHIFT))
#define NDP120_I2C_CONFIG_SR_TXDV_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_SR_TXDV_MASK) >> NDP120_I2C_CONFIG_SR_TXDV_SHIFT)
#define NDP120_I2C_CONFIG_SR_TXDV_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_SR_RXOVF_SHIFT 7
#define NDP120_I2C_CONFIG_SR_RXOVF_MASK 0x00000080U
#define NDP120_I2C_CONFIG_SR_RXOVF(v) \
        ((v) << NDP120_I2C_CONFIG_SR_RXOVF_SHIFT)
#define NDP120_I2C_CONFIG_SR_RXOVF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_SR_RXOVF_SHIFT))
#define NDP120_I2C_CONFIG_SR_RXOVF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_SR_RXOVF_MASK) | ((v) << NDP120_I2C_CONFIG_SR_RXOVF_SHIFT))
#define NDP120_I2C_CONFIG_SR_RXOVF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_SR_RXOVF_MASK) >> NDP120_I2C_CONFIG_SR_RXOVF_SHIFT)
#define NDP120_I2C_CONFIG_SR_RXOVF_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_SR_BA_SHIFT 8
#define NDP120_I2C_CONFIG_SR_BA_MASK 0x00000100U
#define NDP120_I2C_CONFIG_SR_BA(v) \
        ((v) << NDP120_I2C_CONFIG_SR_BA_SHIFT)
#define NDP120_I2C_CONFIG_SR_BA_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_SR_BA_SHIFT))
#define NDP120_I2C_CONFIG_SR_BA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_SR_BA_MASK) | ((v) << NDP120_I2C_CONFIG_SR_BA_SHIFT))
#define NDP120_I2C_CONFIG_SR_BA_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_SR_BA_MASK) >> NDP120_I2C_CONFIG_SR_BA_SHIFT)
#define NDP120_I2C_CONFIG_SR_BA_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_SR_DEFAULT 0x00000000U 
/* register ndp120.i2c_config.ar */
#define NDP120_I2C_CONFIG_AR 0x4000a008U
#define NDP120_I2C_CONFIG_AR_ADDR_SHIFT 0
#define NDP120_I2C_CONFIG_AR_ADDR_MASK 0x000003ffU
#define NDP120_I2C_CONFIG_AR_ADDR(v) \
        ((v) << NDP120_I2C_CONFIG_AR_ADDR_SHIFT)
#define NDP120_I2C_CONFIG_AR_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_AR_ADDR_SHIFT))
#define NDP120_I2C_CONFIG_AR_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_AR_ADDR_MASK) | ((v) << NDP120_I2C_CONFIG_AR_ADDR_SHIFT))
#define NDP120_I2C_CONFIG_AR_ADDR_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_AR_ADDR_MASK) >> NDP120_I2C_CONFIG_AR_ADDR_SHIFT)
#define NDP120_I2C_CONFIG_AR_ADDR_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_AR_DEFAULT 0x00000000U 
/* register ndp120.i2c_config.dr */
#define NDP120_I2C_CONFIG_DR 0x4000a00cU
#define NDP120_I2C_CONFIG_DR_DATA_SHIFT 0
#define NDP120_I2C_CONFIG_DR_DATA_MASK 0x000000ffU
#define NDP120_I2C_CONFIG_DR_DATA(v) \
        ((v) << NDP120_I2C_CONFIG_DR_DATA_SHIFT)
#define NDP120_I2C_CONFIG_DR_DATA_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_DR_DATA_SHIFT))
#define NDP120_I2C_CONFIG_DR_DATA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_DR_DATA_MASK) | ((v) << NDP120_I2C_CONFIG_DR_DATA_SHIFT))
#define NDP120_I2C_CONFIG_DR_DATA_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_DR_DATA_MASK) >> NDP120_I2C_CONFIG_DR_DATA_SHIFT)
#define NDP120_I2C_CONFIG_DR_DATA_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_DR_DEFAULT 0x00000000U 
/* register ndp120.i2c_config.isr */
#define NDP120_I2C_CONFIG_ISR 0x4000a010U
#define NDP120_I2C_CONFIG_ISR_COMP_SHIFT 0
#define NDP120_I2C_CONFIG_ISR_COMP_MASK 0x00000001U
#define NDP120_I2C_CONFIG_ISR_COMP(v) \
        ((v) << NDP120_I2C_CONFIG_ISR_COMP_SHIFT)
#define NDP120_I2C_CONFIG_ISR_COMP_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_ISR_COMP_SHIFT))
#define NDP120_I2C_CONFIG_ISR_COMP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_ISR_COMP_MASK) | ((v) << NDP120_I2C_CONFIG_ISR_COMP_SHIFT))
#define NDP120_I2C_CONFIG_ISR_COMP_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_ISR_COMP_MASK) >> NDP120_I2C_CONFIG_ISR_COMP_SHIFT)
#define NDP120_I2C_CONFIG_ISR_COMP_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_ISR_DATA_SHIFT 1
#define NDP120_I2C_CONFIG_ISR_DATA_MASK 0x00000002U
#define NDP120_I2C_CONFIG_ISR_DATA(v) \
        ((v) << NDP120_I2C_CONFIG_ISR_DATA_SHIFT)
#define NDP120_I2C_CONFIG_ISR_DATA_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_ISR_DATA_SHIFT))
#define NDP120_I2C_CONFIG_ISR_DATA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_ISR_DATA_MASK) | ((v) << NDP120_I2C_CONFIG_ISR_DATA_SHIFT))
#define NDP120_I2C_CONFIG_ISR_DATA_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_ISR_DATA_MASK) >> NDP120_I2C_CONFIG_ISR_DATA_SHIFT)
#define NDP120_I2C_CONFIG_ISR_DATA_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_ISR_NACK_SHIFT 2
#define NDP120_I2C_CONFIG_ISR_NACK_MASK 0x00000004U
#define NDP120_I2C_CONFIG_ISR_NACK(v) \
        ((v) << NDP120_I2C_CONFIG_ISR_NACK_SHIFT)
#define NDP120_I2C_CONFIG_ISR_NACK_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_ISR_NACK_SHIFT))
#define NDP120_I2C_CONFIG_ISR_NACK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_ISR_NACK_MASK) | ((v) << NDP120_I2C_CONFIG_ISR_NACK_SHIFT))
#define NDP120_I2C_CONFIG_ISR_NACK_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_ISR_NACK_MASK) >> NDP120_I2C_CONFIG_ISR_NACK_SHIFT)
#define NDP120_I2C_CONFIG_ISR_NACK_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_ISR_TO_SHIFT 3
#define NDP120_I2C_CONFIG_ISR_TO_MASK 0x00000008U
#define NDP120_I2C_CONFIG_ISR_TO(v) \
        ((v) << NDP120_I2C_CONFIG_ISR_TO_SHIFT)
#define NDP120_I2C_CONFIG_ISR_TO_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_ISR_TO_SHIFT))
#define NDP120_I2C_CONFIG_ISR_TO_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_ISR_TO_MASK) | ((v) << NDP120_I2C_CONFIG_ISR_TO_SHIFT))
#define NDP120_I2C_CONFIG_ISR_TO_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_ISR_TO_MASK) >> NDP120_I2C_CONFIG_ISR_TO_SHIFT)
#define NDP120_I2C_CONFIG_ISR_TO_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_ISR_SLV_RDY_SHIFT 4
#define NDP120_I2C_CONFIG_ISR_SLV_RDY_MASK 0x00000010U
#define NDP120_I2C_CONFIG_ISR_SLV_RDY(v) \
        ((v) << NDP120_I2C_CONFIG_ISR_SLV_RDY_SHIFT)
#define NDP120_I2C_CONFIG_ISR_SLV_RDY_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_ISR_SLV_RDY_SHIFT))
#define NDP120_I2C_CONFIG_ISR_SLV_RDY_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_ISR_SLV_RDY_MASK) | ((v) << NDP120_I2C_CONFIG_ISR_SLV_RDY_SHIFT))
#define NDP120_I2C_CONFIG_ISR_SLV_RDY_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_ISR_SLV_RDY_MASK) >> NDP120_I2C_CONFIG_ISR_SLV_RDY_SHIFT)
#define NDP120_I2C_CONFIG_ISR_SLV_RDY_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_ISR_RX_OVF_SHIFT 5
#define NDP120_I2C_CONFIG_ISR_RX_OVF_MASK 0x00000020U
#define NDP120_I2C_CONFIG_ISR_RX_OVF(v) \
        ((v) << NDP120_I2C_CONFIG_ISR_RX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_ISR_RX_OVF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_ISR_RX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_ISR_RX_OVF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_ISR_RX_OVF_MASK) | ((v) << NDP120_I2C_CONFIG_ISR_RX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_ISR_RX_OVF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_ISR_RX_OVF_MASK) >> NDP120_I2C_CONFIG_ISR_RX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_ISR_RX_OVF_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_ISR_TX_OVF_SHIFT 6
#define NDP120_I2C_CONFIG_ISR_TX_OVF_MASK 0x00000040U
#define NDP120_I2C_CONFIG_ISR_TX_OVF(v) \
        ((v) << NDP120_I2C_CONFIG_ISR_TX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_ISR_TX_OVF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_ISR_TX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_ISR_TX_OVF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_ISR_TX_OVF_MASK) | ((v) << NDP120_I2C_CONFIG_ISR_TX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_ISR_TX_OVF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_ISR_TX_OVF_MASK) >> NDP120_I2C_CONFIG_ISR_TX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_ISR_TX_OVF_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_ISR_RX_UNF_SHIFT 7
#define NDP120_I2C_CONFIG_ISR_RX_UNF_MASK 0x00000080U
#define NDP120_I2C_CONFIG_ISR_RX_UNF(v) \
        ((v) << NDP120_I2C_CONFIG_ISR_RX_UNF_SHIFT)
#define NDP120_I2C_CONFIG_ISR_RX_UNF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_ISR_RX_UNF_SHIFT))
#define NDP120_I2C_CONFIG_ISR_RX_UNF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_ISR_RX_UNF_MASK) | ((v) << NDP120_I2C_CONFIG_ISR_RX_UNF_SHIFT))
#define NDP120_I2C_CONFIG_ISR_RX_UNF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_ISR_RX_UNF_MASK) >> NDP120_I2C_CONFIG_ISR_RX_UNF_SHIFT)
#define NDP120_I2C_CONFIG_ISR_RX_UNF_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_ISR_ARB_LOST_SHIFT 9
#define NDP120_I2C_CONFIG_ISR_ARB_LOST_MASK 0x00000200U
#define NDP120_I2C_CONFIG_ISR_ARB_LOST(v) \
        ((v) << NDP120_I2C_CONFIG_ISR_ARB_LOST_SHIFT)
#define NDP120_I2C_CONFIG_ISR_ARB_LOST_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_ISR_ARB_LOST_SHIFT))
#define NDP120_I2C_CONFIG_ISR_ARB_LOST_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_ISR_ARB_LOST_MASK) | ((v) << NDP120_I2C_CONFIG_ISR_ARB_LOST_SHIFT))
#define NDP120_I2C_CONFIG_ISR_ARB_LOST_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_ISR_ARB_LOST_MASK) >> NDP120_I2C_CONFIG_ISR_ARB_LOST_SHIFT)
#define NDP120_I2C_CONFIG_ISR_ARB_LOST_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_ISR_DEFAULT 0x00000000U 
/* register ndp120.i2c_config.tsr */
#define NDP120_I2C_CONFIG_TSR 0x4000a014U
#define NDP120_I2C_CONFIG_TSR_TR_SIZE_SHIFT 0
#define NDP120_I2C_CONFIG_TSR_TR_SIZE_MASK 0x0000001fU
#define NDP120_I2C_CONFIG_TSR_TR_SIZE(v) \
        ((v) << NDP120_I2C_CONFIG_TSR_TR_SIZE_SHIFT)
#define NDP120_I2C_CONFIG_TSR_TR_SIZE_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_TSR_TR_SIZE_SHIFT))
#define NDP120_I2C_CONFIG_TSR_TR_SIZE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_TSR_TR_SIZE_MASK) | ((v) << NDP120_I2C_CONFIG_TSR_TR_SIZE_SHIFT))
#define NDP120_I2C_CONFIG_TSR_TR_SIZE_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_TSR_TR_SIZE_MASK) >> NDP120_I2C_CONFIG_TSR_TR_SIZE_SHIFT)
#define NDP120_I2C_CONFIG_TSR_TR_SIZE_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_TSR_DEFAULT 0x00000000U 
/* register ndp120.i2c_config.smpr */
#define NDP120_I2C_CONFIG_SMPR 0x4000a018U
#define NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_SHIFT 0
#define NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_MASK 0x0000000fU
#define NDP120_I2C_CONFIG_SMPR_PAUSE_INTER(v) \
        ((v) << NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_SHIFT)
#define NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_SHIFT))
#define NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_MASK) | ((v) << NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_SHIFT))
#define NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_MASK) >> NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_SHIFT)
#define NDP120_I2C_CONFIG_SMPR_PAUSE_INTER_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_SMPR_DEFAULT 0x00000000U 
/* register ndp120.i2c_config.tor */
#define NDP120_I2C_CONFIG_TOR 0x4000a01cU
#define NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_SHIFT 0
#define NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_MASK 0x000000ffU
#define NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI(v) \
        ((v) << NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_SHIFT)
#define NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_SHIFT))
#define NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_MASK) | ((v) << NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_SHIFT))
#define NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_MASK) >> NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_SHIFT)
#define NDP120_I2C_CONFIG_TOR_DLF_TRACK_KI_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_TOR_DEFAULT 0x00000000U 
/* register ndp120.i2c_config.imr */
#define NDP120_I2C_CONFIG_IMR 0x4000a020U
#define NDP120_I2C_CONFIG_IMR_COMP_SHIFT 0
#define NDP120_I2C_CONFIG_IMR_COMP_MASK 0x00000001U
#define NDP120_I2C_CONFIG_IMR_COMP(v) \
        ((v) << NDP120_I2C_CONFIG_IMR_COMP_SHIFT)
#define NDP120_I2C_CONFIG_IMR_COMP_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IMR_COMP_SHIFT))
#define NDP120_I2C_CONFIG_IMR_COMP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IMR_COMP_MASK) | ((v) << NDP120_I2C_CONFIG_IMR_COMP_SHIFT))
#define NDP120_I2C_CONFIG_IMR_COMP_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IMR_COMP_MASK) >> NDP120_I2C_CONFIG_IMR_COMP_SHIFT)
#define NDP120_I2C_CONFIG_IMR_COMP_DEFAULT 0x00000001U
#define NDP120_I2C_CONFIG_IMR_DATA_SHIFT 1
#define NDP120_I2C_CONFIG_IMR_DATA_MASK 0x00000002U
#define NDP120_I2C_CONFIG_IMR_DATA(v) \
        ((v) << NDP120_I2C_CONFIG_IMR_DATA_SHIFT)
#define NDP120_I2C_CONFIG_IMR_DATA_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IMR_DATA_SHIFT))
#define NDP120_I2C_CONFIG_IMR_DATA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IMR_DATA_MASK) | ((v) << NDP120_I2C_CONFIG_IMR_DATA_SHIFT))
#define NDP120_I2C_CONFIG_IMR_DATA_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IMR_DATA_MASK) >> NDP120_I2C_CONFIG_IMR_DATA_SHIFT)
#define NDP120_I2C_CONFIG_IMR_DATA_DEFAULT 0x00000001U
#define NDP120_I2C_CONFIG_IMR_NACK_SHIFT 2
#define NDP120_I2C_CONFIG_IMR_NACK_MASK 0x00000004U
#define NDP120_I2C_CONFIG_IMR_NACK(v) \
        ((v) << NDP120_I2C_CONFIG_IMR_NACK_SHIFT)
#define NDP120_I2C_CONFIG_IMR_NACK_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IMR_NACK_SHIFT))
#define NDP120_I2C_CONFIG_IMR_NACK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IMR_NACK_MASK) | ((v) << NDP120_I2C_CONFIG_IMR_NACK_SHIFT))
#define NDP120_I2C_CONFIG_IMR_NACK_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IMR_NACK_MASK) >> NDP120_I2C_CONFIG_IMR_NACK_SHIFT)
#define NDP120_I2C_CONFIG_IMR_NACK_DEFAULT 0x00000001U
#define NDP120_I2C_CONFIG_IMR_TO_SHIFT 3
#define NDP120_I2C_CONFIG_IMR_TO_MASK 0x00000008U
#define NDP120_I2C_CONFIG_IMR_TO(v) \
        ((v) << NDP120_I2C_CONFIG_IMR_TO_SHIFT)
#define NDP120_I2C_CONFIG_IMR_TO_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IMR_TO_SHIFT))
#define NDP120_I2C_CONFIG_IMR_TO_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IMR_TO_MASK) | ((v) << NDP120_I2C_CONFIG_IMR_TO_SHIFT))
#define NDP120_I2C_CONFIG_IMR_TO_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IMR_TO_MASK) >> NDP120_I2C_CONFIG_IMR_TO_SHIFT)
#define NDP120_I2C_CONFIG_IMR_TO_DEFAULT 0x00000001U
#define NDP120_I2C_CONFIG_IMR_SLV_RDY_SHIFT 4
#define NDP120_I2C_CONFIG_IMR_SLV_RDY_MASK 0x00000010U
#define NDP120_I2C_CONFIG_IMR_SLV_RDY(v) \
        ((v) << NDP120_I2C_CONFIG_IMR_SLV_RDY_SHIFT)
#define NDP120_I2C_CONFIG_IMR_SLV_RDY_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IMR_SLV_RDY_SHIFT))
#define NDP120_I2C_CONFIG_IMR_SLV_RDY_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IMR_SLV_RDY_MASK) | ((v) << NDP120_I2C_CONFIG_IMR_SLV_RDY_SHIFT))
#define NDP120_I2C_CONFIG_IMR_SLV_RDY_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IMR_SLV_RDY_MASK) >> NDP120_I2C_CONFIG_IMR_SLV_RDY_SHIFT)
#define NDP120_I2C_CONFIG_IMR_SLV_RDY_DEFAULT 0x00000001U
#define NDP120_I2C_CONFIG_IMR_RX_OVF_SHIFT 5
#define NDP120_I2C_CONFIG_IMR_RX_OVF_MASK 0x00000020U
#define NDP120_I2C_CONFIG_IMR_RX_OVF(v) \
        ((v) << NDP120_I2C_CONFIG_IMR_RX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IMR_RX_OVF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IMR_RX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IMR_RX_OVF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IMR_RX_OVF_MASK) | ((v) << NDP120_I2C_CONFIG_IMR_RX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IMR_RX_OVF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IMR_RX_OVF_MASK) >> NDP120_I2C_CONFIG_IMR_RX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IMR_RX_OVF_DEFAULT 0x00000001U
#define NDP120_I2C_CONFIG_IMR_TX_OVF_SHIFT 6
#define NDP120_I2C_CONFIG_IMR_TX_OVF_MASK 0x00000040U
#define NDP120_I2C_CONFIG_IMR_TX_OVF(v) \
        ((v) << NDP120_I2C_CONFIG_IMR_TX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IMR_TX_OVF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IMR_TX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IMR_TX_OVF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IMR_TX_OVF_MASK) | ((v) << NDP120_I2C_CONFIG_IMR_TX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IMR_TX_OVF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IMR_TX_OVF_MASK) >> NDP120_I2C_CONFIG_IMR_TX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IMR_TX_OVF_DEFAULT 0x00000001U
#define NDP120_I2C_CONFIG_IMR_RX_UNF_SHIFT 7
#define NDP120_I2C_CONFIG_IMR_RX_UNF_MASK 0x00000080U
#define NDP120_I2C_CONFIG_IMR_RX_UNF(v) \
        ((v) << NDP120_I2C_CONFIG_IMR_RX_UNF_SHIFT)
#define NDP120_I2C_CONFIG_IMR_RX_UNF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IMR_RX_UNF_SHIFT))
#define NDP120_I2C_CONFIG_IMR_RX_UNF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IMR_RX_UNF_MASK) | ((v) << NDP120_I2C_CONFIG_IMR_RX_UNF_SHIFT))
#define NDP120_I2C_CONFIG_IMR_RX_UNF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IMR_RX_UNF_MASK) >> NDP120_I2C_CONFIG_IMR_RX_UNF_SHIFT)
#define NDP120_I2C_CONFIG_IMR_RX_UNF_DEFAULT 0x00000001U
#define NDP120_I2C_CONFIG_IMR_ARB_LOST_SHIFT 9
#define NDP120_I2C_CONFIG_IMR_ARB_LOST_MASK 0x00000200U
#define NDP120_I2C_CONFIG_IMR_ARB_LOST(v) \
        ((v) << NDP120_I2C_CONFIG_IMR_ARB_LOST_SHIFT)
#define NDP120_I2C_CONFIG_IMR_ARB_LOST_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IMR_ARB_LOST_SHIFT))
#define NDP120_I2C_CONFIG_IMR_ARB_LOST_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IMR_ARB_LOST_MASK) | ((v) << NDP120_I2C_CONFIG_IMR_ARB_LOST_SHIFT))
#define NDP120_I2C_CONFIG_IMR_ARB_LOST_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IMR_ARB_LOST_MASK) >> NDP120_I2C_CONFIG_IMR_ARB_LOST_SHIFT)
#define NDP120_I2C_CONFIG_IMR_ARB_LOST_DEFAULT 0x00000001U
#define NDP120_I2C_CONFIG_IMR_DEFAULT 0x000002ffU 
/* register ndp120.i2c_config.ier */
#define NDP120_I2C_CONFIG_IER 0x4000a024U
#define NDP120_I2C_CONFIG_IER_COMP_SHIFT 0
#define NDP120_I2C_CONFIG_IER_COMP_MASK 0x00000001U
#define NDP120_I2C_CONFIG_IER_COMP(v) \
        ((v) << NDP120_I2C_CONFIG_IER_COMP_SHIFT)
#define NDP120_I2C_CONFIG_IER_COMP_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IER_COMP_SHIFT))
#define NDP120_I2C_CONFIG_IER_COMP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IER_COMP_MASK) | ((v) << NDP120_I2C_CONFIG_IER_COMP_SHIFT))
#define NDP120_I2C_CONFIG_IER_COMP_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IER_COMP_MASK) >> NDP120_I2C_CONFIG_IER_COMP_SHIFT)
#define NDP120_I2C_CONFIG_IER_COMP_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IER_DATA_SHIFT 1
#define NDP120_I2C_CONFIG_IER_DATA_MASK 0x00000002U
#define NDP120_I2C_CONFIG_IER_DATA(v) \
        ((v) << NDP120_I2C_CONFIG_IER_DATA_SHIFT)
#define NDP120_I2C_CONFIG_IER_DATA_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IER_DATA_SHIFT))
#define NDP120_I2C_CONFIG_IER_DATA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IER_DATA_MASK) | ((v) << NDP120_I2C_CONFIG_IER_DATA_SHIFT))
#define NDP120_I2C_CONFIG_IER_DATA_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IER_DATA_MASK) >> NDP120_I2C_CONFIG_IER_DATA_SHIFT)
#define NDP120_I2C_CONFIG_IER_DATA_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IER_NACK_SHIFT 2
#define NDP120_I2C_CONFIG_IER_NACK_MASK 0x00000004U
#define NDP120_I2C_CONFIG_IER_NACK(v) \
        ((v) << NDP120_I2C_CONFIG_IER_NACK_SHIFT)
#define NDP120_I2C_CONFIG_IER_NACK_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IER_NACK_SHIFT))
#define NDP120_I2C_CONFIG_IER_NACK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IER_NACK_MASK) | ((v) << NDP120_I2C_CONFIG_IER_NACK_SHIFT))
#define NDP120_I2C_CONFIG_IER_NACK_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IER_NACK_MASK) >> NDP120_I2C_CONFIG_IER_NACK_SHIFT)
#define NDP120_I2C_CONFIG_IER_NACK_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IER_TO_SHIFT 3
#define NDP120_I2C_CONFIG_IER_TO_MASK 0x00000008U
#define NDP120_I2C_CONFIG_IER_TO(v) \
        ((v) << NDP120_I2C_CONFIG_IER_TO_SHIFT)
#define NDP120_I2C_CONFIG_IER_TO_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IER_TO_SHIFT))
#define NDP120_I2C_CONFIG_IER_TO_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IER_TO_MASK) | ((v) << NDP120_I2C_CONFIG_IER_TO_SHIFT))
#define NDP120_I2C_CONFIG_IER_TO_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IER_TO_MASK) >> NDP120_I2C_CONFIG_IER_TO_SHIFT)
#define NDP120_I2C_CONFIG_IER_TO_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IER_SLV_RDY_SHIFT 4
#define NDP120_I2C_CONFIG_IER_SLV_RDY_MASK 0x00000010U
#define NDP120_I2C_CONFIG_IER_SLV_RDY(v) \
        ((v) << NDP120_I2C_CONFIG_IER_SLV_RDY_SHIFT)
#define NDP120_I2C_CONFIG_IER_SLV_RDY_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IER_SLV_RDY_SHIFT))
#define NDP120_I2C_CONFIG_IER_SLV_RDY_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IER_SLV_RDY_MASK) | ((v) << NDP120_I2C_CONFIG_IER_SLV_RDY_SHIFT))
#define NDP120_I2C_CONFIG_IER_SLV_RDY_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IER_SLV_RDY_MASK) >> NDP120_I2C_CONFIG_IER_SLV_RDY_SHIFT)
#define NDP120_I2C_CONFIG_IER_SLV_RDY_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IER_RX_OVF_SHIFT 5
#define NDP120_I2C_CONFIG_IER_RX_OVF_MASK 0x00000020U
#define NDP120_I2C_CONFIG_IER_RX_OVF(v) \
        ((v) << NDP120_I2C_CONFIG_IER_RX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IER_RX_OVF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IER_RX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IER_RX_OVF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IER_RX_OVF_MASK) | ((v) << NDP120_I2C_CONFIG_IER_RX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IER_RX_OVF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IER_RX_OVF_MASK) >> NDP120_I2C_CONFIG_IER_RX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IER_RX_OVF_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IER_TX_OVF_SHIFT 6
#define NDP120_I2C_CONFIG_IER_TX_OVF_MASK 0x00000040U
#define NDP120_I2C_CONFIG_IER_TX_OVF(v) \
        ((v) << NDP120_I2C_CONFIG_IER_TX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IER_TX_OVF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IER_TX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IER_TX_OVF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IER_TX_OVF_MASK) | ((v) << NDP120_I2C_CONFIG_IER_TX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IER_TX_OVF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IER_TX_OVF_MASK) >> NDP120_I2C_CONFIG_IER_TX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IER_TX_OVF_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IER_RX_UNF_SHIFT 7
#define NDP120_I2C_CONFIG_IER_RX_UNF_MASK 0x00000080U
#define NDP120_I2C_CONFIG_IER_RX_UNF(v) \
        ((v) << NDP120_I2C_CONFIG_IER_RX_UNF_SHIFT)
#define NDP120_I2C_CONFIG_IER_RX_UNF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IER_RX_UNF_SHIFT))
#define NDP120_I2C_CONFIG_IER_RX_UNF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IER_RX_UNF_MASK) | ((v) << NDP120_I2C_CONFIG_IER_RX_UNF_SHIFT))
#define NDP120_I2C_CONFIG_IER_RX_UNF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IER_RX_UNF_MASK) >> NDP120_I2C_CONFIG_IER_RX_UNF_SHIFT)
#define NDP120_I2C_CONFIG_IER_RX_UNF_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IER_ARB_LOST_SHIFT 9
#define NDP120_I2C_CONFIG_IER_ARB_LOST_MASK 0x00000200U
#define NDP120_I2C_CONFIG_IER_ARB_LOST(v) \
        ((v) << NDP120_I2C_CONFIG_IER_ARB_LOST_SHIFT)
#define NDP120_I2C_CONFIG_IER_ARB_LOST_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IER_ARB_LOST_SHIFT))
#define NDP120_I2C_CONFIG_IER_ARB_LOST_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IER_ARB_LOST_MASK) | ((v) << NDP120_I2C_CONFIG_IER_ARB_LOST_SHIFT))
#define NDP120_I2C_CONFIG_IER_ARB_LOST_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IER_ARB_LOST_MASK) >> NDP120_I2C_CONFIG_IER_ARB_LOST_SHIFT)
#define NDP120_I2C_CONFIG_IER_ARB_LOST_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IER_DEFAULT 0x00000000U 
/* register ndp120.i2c_config.idr */
#define NDP120_I2C_CONFIG_IDR 0x4000a028U
#define NDP120_I2C_CONFIG_IDR_COMP_SHIFT 0
#define NDP120_I2C_CONFIG_IDR_COMP_MASK 0x00000001U
#define NDP120_I2C_CONFIG_IDR_COMP(v) \
        ((v) << NDP120_I2C_CONFIG_IDR_COMP_SHIFT)
#define NDP120_I2C_CONFIG_IDR_COMP_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IDR_COMP_SHIFT))
#define NDP120_I2C_CONFIG_IDR_COMP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IDR_COMP_MASK) | ((v) << NDP120_I2C_CONFIG_IDR_COMP_SHIFT))
#define NDP120_I2C_CONFIG_IDR_COMP_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IDR_COMP_MASK) >> NDP120_I2C_CONFIG_IDR_COMP_SHIFT)
#define NDP120_I2C_CONFIG_IDR_COMP_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IDR_DATA_SHIFT 1
#define NDP120_I2C_CONFIG_IDR_DATA_MASK 0x00000002U
#define NDP120_I2C_CONFIG_IDR_DATA(v) \
        ((v) << NDP120_I2C_CONFIG_IDR_DATA_SHIFT)
#define NDP120_I2C_CONFIG_IDR_DATA_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IDR_DATA_SHIFT))
#define NDP120_I2C_CONFIG_IDR_DATA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IDR_DATA_MASK) | ((v) << NDP120_I2C_CONFIG_IDR_DATA_SHIFT))
#define NDP120_I2C_CONFIG_IDR_DATA_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IDR_DATA_MASK) >> NDP120_I2C_CONFIG_IDR_DATA_SHIFT)
#define NDP120_I2C_CONFIG_IDR_DATA_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IDR_NACK_SHIFT 2
#define NDP120_I2C_CONFIG_IDR_NACK_MASK 0x00000004U
#define NDP120_I2C_CONFIG_IDR_NACK(v) \
        ((v) << NDP120_I2C_CONFIG_IDR_NACK_SHIFT)
#define NDP120_I2C_CONFIG_IDR_NACK_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IDR_NACK_SHIFT))
#define NDP120_I2C_CONFIG_IDR_NACK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IDR_NACK_MASK) | ((v) << NDP120_I2C_CONFIG_IDR_NACK_SHIFT))
#define NDP120_I2C_CONFIG_IDR_NACK_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IDR_NACK_MASK) >> NDP120_I2C_CONFIG_IDR_NACK_SHIFT)
#define NDP120_I2C_CONFIG_IDR_NACK_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IDR_TO_SHIFT 3
#define NDP120_I2C_CONFIG_IDR_TO_MASK 0x00000008U
#define NDP120_I2C_CONFIG_IDR_TO(v) \
        ((v) << NDP120_I2C_CONFIG_IDR_TO_SHIFT)
#define NDP120_I2C_CONFIG_IDR_TO_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IDR_TO_SHIFT))
#define NDP120_I2C_CONFIG_IDR_TO_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IDR_TO_MASK) | ((v) << NDP120_I2C_CONFIG_IDR_TO_SHIFT))
#define NDP120_I2C_CONFIG_IDR_TO_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IDR_TO_MASK) >> NDP120_I2C_CONFIG_IDR_TO_SHIFT)
#define NDP120_I2C_CONFIG_IDR_TO_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IDR_SLV_RDY_SHIFT 4
#define NDP120_I2C_CONFIG_IDR_SLV_RDY_MASK 0x00000010U
#define NDP120_I2C_CONFIG_IDR_SLV_RDY(v) \
        ((v) << NDP120_I2C_CONFIG_IDR_SLV_RDY_SHIFT)
#define NDP120_I2C_CONFIG_IDR_SLV_RDY_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IDR_SLV_RDY_SHIFT))
#define NDP120_I2C_CONFIG_IDR_SLV_RDY_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IDR_SLV_RDY_MASK) | ((v) << NDP120_I2C_CONFIG_IDR_SLV_RDY_SHIFT))
#define NDP120_I2C_CONFIG_IDR_SLV_RDY_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IDR_SLV_RDY_MASK) >> NDP120_I2C_CONFIG_IDR_SLV_RDY_SHIFT)
#define NDP120_I2C_CONFIG_IDR_SLV_RDY_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IDR_RX_OVF_SHIFT 5
#define NDP120_I2C_CONFIG_IDR_RX_OVF_MASK 0x00000020U
#define NDP120_I2C_CONFIG_IDR_RX_OVF(v) \
        ((v) << NDP120_I2C_CONFIG_IDR_RX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IDR_RX_OVF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IDR_RX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IDR_RX_OVF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IDR_RX_OVF_MASK) | ((v) << NDP120_I2C_CONFIG_IDR_RX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IDR_RX_OVF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IDR_RX_OVF_MASK) >> NDP120_I2C_CONFIG_IDR_RX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IDR_RX_OVF_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IDR_TX_OVF_SHIFT 6
#define NDP120_I2C_CONFIG_IDR_TX_OVF_MASK 0x00000040U
#define NDP120_I2C_CONFIG_IDR_TX_OVF(v) \
        ((v) << NDP120_I2C_CONFIG_IDR_TX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IDR_TX_OVF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IDR_TX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IDR_TX_OVF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IDR_TX_OVF_MASK) | ((v) << NDP120_I2C_CONFIG_IDR_TX_OVF_SHIFT))
#define NDP120_I2C_CONFIG_IDR_TX_OVF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IDR_TX_OVF_MASK) >> NDP120_I2C_CONFIG_IDR_TX_OVF_SHIFT)
#define NDP120_I2C_CONFIG_IDR_TX_OVF_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IDR_RX_UNF_SHIFT 7
#define NDP120_I2C_CONFIG_IDR_RX_UNF_MASK 0x00000080U
#define NDP120_I2C_CONFIG_IDR_RX_UNF(v) \
        ((v) << NDP120_I2C_CONFIG_IDR_RX_UNF_SHIFT)
#define NDP120_I2C_CONFIG_IDR_RX_UNF_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IDR_RX_UNF_SHIFT))
#define NDP120_I2C_CONFIG_IDR_RX_UNF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IDR_RX_UNF_MASK) | ((v) << NDP120_I2C_CONFIG_IDR_RX_UNF_SHIFT))
#define NDP120_I2C_CONFIG_IDR_RX_UNF_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IDR_RX_UNF_MASK) >> NDP120_I2C_CONFIG_IDR_RX_UNF_SHIFT)
#define NDP120_I2C_CONFIG_IDR_RX_UNF_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IDR_ARB_LOST_SHIFT 9
#define NDP120_I2C_CONFIG_IDR_ARB_LOST_MASK 0x00000200U
#define NDP120_I2C_CONFIG_IDR_ARB_LOST(v) \
        ((v) << NDP120_I2C_CONFIG_IDR_ARB_LOST_SHIFT)
#define NDP120_I2C_CONFIG_IDR_ARB_LOST_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_IDR_ARB_LOST_SHIFT))
#define NDP120_I2C_CONFIG_IDR_ARB_LOST_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_IDR_ARB_LOST_MASK) | ((v) << NDP120_I2C_CONFIG_IDR_ARB_LOST_SHIFT))
#define NDP120_I2C_CONFIG_IDR_ARB_LOST_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_IDR_ARB_LOST_MASK) >> NDP120_I2C_CONFIG_IDR_ARB_LOST_SHIFT)
#define NDP120_I2C_CONFIG_IDR_ARB_LOST_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_IDR_DEFAULT 0x00000000U 
/* register ndp120.i2c_config.gfcr */
#define NDP120_I2C_CONFIG_GFCR 0x4000a02cU
#define NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_SHIFT 0
#define NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_MASK 0x0000000fU
#define NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH(v) \
        ((v) << NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_SHIFT)
#define NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_INSERT(x, v) \
        ((x) | ((v) << NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_SHIFT))
#define NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_MASK_INSERT(x, v) \
        (((x) & ~NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_MASK) | ((v) << NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_SHIFT))
#define NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_EXTRACT(x) \
        (((x) & NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_MASK) >> NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_SHIFT)
#define NDP120_I2C_CONFIG_GFCR_GFILTER_DEPTH_DEFAULT 0x00000000U
#define NDP120_I2C_CONFIG_GFCR_DEFAULT 0x00000000U 

/*
 * block ndp120.dsp_config, base 0x4000c000
 */
#define NDP120_DSP_CONFIG 0x4000c000U
#define NDP120_DSP_CONFIG_SIZE 0x00001000U
/* register ndp120.dsp_config.id */
#define NDP120_DSP_CONFIG_ID 0x4000c000U
/* register array ndp120.dsp_config.pdmctl[2] */
#define NDP120_DSP_CONFIG_PDMCTL(i) (0x4000c004U + ((i) << 2))
#define NDP120_DSP_CONFIG_PDMCTL_COUNT 2
#define NDP120_DSP_CONFIG_PDMCTL_RSTB_SHIFT 0
#define NDP120_DSP_CONFIG_PDMCTL_RSTB_MASK 0x00000001U
#define NDP120_DSP_CONFIG_PDMCTL_RSTB(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCTL_RSTB_SHIFT)
#define NDP120_DSP_CONFIG_PDMCTL_RSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCTL_RSTB_SHIFT))
#define NDP120_DSP_CONFIG_PDMCTL_RSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCTL_RSTB_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCTL_RSTB_SHIFT))
#define NDP120_DSP_CONFIG_PDMCTL_RSTB_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCTL_RSTB_MASK) >> NDP120_DSP_CONFIG_PDMCTL_RSTB_SHIFT)
#define NDP120_DSP_CONFIG_PDMCTL_RSTB_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_PDMCTL_ENABLE_SHIFT 1
#define NDP120_DSP_CONFIG_PDMCTL_ENABLE_MASK 0x00000002U
#define NDP120_DSP_CONFIG_PDMCTL_ENABLE(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCTL_ENABLE_SHIFT)
#define NDP120_DSP_CONFIG_PDMCTL_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCTL_ENABLE_SHIFT))
#define NDP120_DSP_CONFIG_PDMCTL_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCTL_ENABLE_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCTL_ENABLE_SHIFT))
#define NDP120_DSP_CONFIG_PDMCTL_ENABLE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCTL_ENABLE_MASK) >> NDP120_DSP_CONFIG_PDMCTL_ENABLE_SHIFT)
#define NDP120_DSP_CONFIG_PDMCTL_ENABLE_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_SHIFT 2
#define NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_MASK 0x00000004U
#define NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_SHIFT)
#define NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_SHIFT))
#define NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_SHIFT))
#define NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_MASK) >> NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_SHIFT)
#define NDP120_DSP_CONFIG_PDMCTL_POSEDGEENABLE_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_SHIFT 3
#define NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_MASK 0x00000008U
#define NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_SHIFT)
#define NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_SHIFT))
#define NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_SHIFT))
#define NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_MASK) >> NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_SHIFT)
#define NDP120_DSP_CONFIG_PDMCTL_NEGEDGEENABLE_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_PDMCTL_UPDATE_SHIFT 4
#define NDP120_DSP_CONFIG_PDMCTL_UPDATE_MASK 0x00000010U
#define NDP120_DSP_CONFIG_PDMCTL_UPDATE(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCTL_UPDATE_SHIFT)
#define NDP120_DSP_CONFIG_PDMCTL_UPDATE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCTL_UPDATE_SHIFT))
#define NDP120_DSP_CONFIG_PDMCTL_UPDATE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCTL_UPDATE_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCTL_UPDATE_SHIFT))
#define NDP120_DSP_CONFIG_PDMCTL_UPDATE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCTL_UPDATE_MASK) >> NDP120_DSP_CONFIG_PDMCTL_UPDATE_SHIFT)
#define NDP120_DSP_CONFIG_PDMCTL_UPDATE_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_PDMCTL_DEFAULT 0x00000000U 
/* register array ndp120.dsp_config.pdmcfg_a[2] */
#define NDP120_DSP_CONFIG_PDMCFG_A(i) (0x4000c00cU + ((i) << 2))
#define NDP120_DSP_CONFIG_PDMCFG_A_COUNT 2
#define NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_SHIFT 0
#define NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_MASK 0x000000ffU
#define NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_MASK) >> NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_A_DECIMATION_DEFAULT 0x00000030U
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_SHIFT 8
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_MASK 0x00000100U
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_MASK) >> NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMBYPASS_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_SHIFT 9
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_MASK 0x00000200U
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_MASK) >> NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_A_PDMFILTSTAGE2BYPASS_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_PDMCFG_A_DEFAULT 0x00000030U 
/* register array ndp120.dsp_config.i2sctl[3] */
#define NDP120_DSP_CONFIG_I2SCTL(i) (0x4000c014U + ((i) << 2))
#define NDP120_DSP_CONFIG_I2SCTL_COUNT 3
#define NDP120_DSP_CONFIG_I2SCTL_ENABLE_SHIFT 0
#define NDP120_DSP_CONFIG_I2SCTL_ENABLE_MASK 0x00000001U
#define NDP120_DSP_CONFIG_I2SCTL_ENABLE(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_ENABLE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_ENABLE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_ENABLE_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_ENABLE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_ENABLE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_ENABLE_MASK) >> NDP120_DSP_CONFIG_I2SCTL_ENABLE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_ENABLE_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_I2SCTL_INIT_SHIFT 1
#define NDP120_DSP_CONFIG_I2SCTL_INIT_MASK 0x00000002U
#define NDP120_DSP_CONFIG_I2SCTL_INIT(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_INIT_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_INIT_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_INIT_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_INIT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_INIT_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_INIT_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_INIT_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_INIT_MASK) >> NDP120_DSP_CONFIG_I2SCTL_INIT_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_INIT_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_I2SCTL_MODE_SHIFT 2
#define NDP120_DSP_CONFIG_I2SCTL_MODE_MASK 0x0000000cU
#define NDP120_DSP_CONFIG_I2SCTL_MODE(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_MODE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_MODE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_MODE_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_MODE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_MODE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_MODE_MASK) >> NDP120_DSP_CONFIG_I2SCTL_MODE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_MODE_DEFAULT 0x00000003U
#define NDP120_DSP_CONFIG_I2SCTL_PACKED_SHIFT 4
#define NDP120_DSP_CONFIG_I2SCTL_PACKED_MASK 0x00000010U
#define NDP120_DSP_CONFIG_I2SCTL_PACKED(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_PACKED_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_PACKED_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_PACKED_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_PACKED_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_PACKED_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_PACKED_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_PACKED_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_PACKED_MASK) >> NDP120_DSP_CONFIG_I2SCTL_PACKED_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_PACKED_DEFAULT 0x00000001U
#define NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_SHIFT 5
#define NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_MASK 0x00000020U
#define NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_MASK) >> NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_RIGHTCHENABLE_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_SHIFT 6
#define NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_MASK 0x00000040U
#define NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_MASK) >> NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_LEFTCHENABLE_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_SHIFT 7
#define NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_MASK 0x00001f80U
#define NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_MASK) >> NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_FRAMESIZE_DEFAULT 0x0000001fU
#define NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_SHIFT 13
#define NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_MASK 0x0007e000U
#define NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_MASK) >> NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_SAMPLESIZE_DEFAULT 0x0000001fU
#define NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_SHIFT 19
#define NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_MASK 0x01f80000U
#define NDP120_DSP_CONFIG_I2SCTL_MSBINDEX(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_MASK) >> NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_MSBINDEX_DEFAULT 0x0000001fU
#define NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_SHIFT 25
#define NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_MASK 0x02000000U
#define NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_MASK) >> NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_NEGEDGEENABLE_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_SHIFT 26
#define NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_MASK 0x04000000U
#define NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_MASK) >> NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_DELAYEDFLOPSENSITIVITY_DEFAULT 0x00000001U
#define NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_SHIFT 27
#define NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_MASK 0x08000000U
#define NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_MASK) >> NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_AUDIO_OUT_FS_EXT_ENABLE_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_SHIFT 28
#define NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_MASK 0x10000000U
#define NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM(v) \
        ((v) << NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_MASK) | ((v) << NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_SHIFT))
#define NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_MASK) >> NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_SHIFT)
#define NDP120_DSP_CONFIG_I2SCTL_DUALCHANTDM_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_I2SCTL_DEFAULT 0x04fbef9cU 
/* register array ndp120.dsp_config.pdmcfg_b[4] */
#define NDP120_DSP_CONFIG_PDMCFG_B(i) (0x4000c020U + ((i) << 2))
#define NDP120_DSP_CONFIG_PDMCFG_B_COUNT 4
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_SHIFT 0
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_MASK 0x00000003U
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_MASK) >> NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_OFF 0x0U
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_STATIC 0x1U
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_ON 0x2U
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_MAX 0x2U
#define NDP120_DSP_CONFIG_PDMCFG_B_DCREMOVALMODE_VALID(v) \
        (v >= 0 && v <= 2)
#define NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_SHIFT 2
#define NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_MASK 0x003ffffcU
#define NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_MASK) >> NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_DCSTATICREMVAL_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL_SHIFT 22
#define NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL_MASK 0x00400000U
#define NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL_MASK) >> NDP120_DSP_CONFIG_PDMCFG_B_CIC_FAIL_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_SATURATED_SHIFT 23
#define NDP120_DSP_CONFIG_PDMCFG_B_SATURATED_MASK 0x00800000U
#define NDP120_DSP_CONFIG_PDMCFG_B_SATURATED(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCFG_B_SATURATED_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_SATURATED_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_SATURATED_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_SATURATED_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCFG_B_SATURATED_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_SATURATED_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_SATURATED_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCFG_B_SATURATED_MASK) >> NDP120_DSP_CONFIG_PDMCFG_B_SATURATED_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_SHIFT 24
#define NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_MASK 0x1f000000U
#define NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_MASK) >> NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_INSHIFT_DEFAULT 0x0000000aU
#define NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_SHIFT 29
#define NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_MASK 0xe0000000U
#define NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT(v) \
        ((v) << NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_MASK) | ((v) << NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_SHIFT))
#define NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_MASK) >> NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_SHIFT)
#define NDP120_DSP_CONFIG_PDMCFG_B_OUTSHIFT_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_PDMCFG_B_DEFAULT 0x0a000000U 
/* register array ndp120.dsp_config.bwcoef_a0_cfg[4] */
#define NDP120_DSP_CONFIG_BWCOEF_A0_CFG(i) (0x4000c030U + ((i) << 2))
#define NDP120_DSP_CONFIG_BWCOEF_A0_CFG_COUNT 4
#define NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_SHIFT 0
#define NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_MASK 0x00ffffffU
#define NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0(v) \
        ((v) << NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_MASK) | ((v) << NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_MASK) >> NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_A0_CFG_BWCOEF_A0_DEFAULT 0x00400000U
#define NDP120_DSP_CONFIG_BWCOEF_A0_CFG_DEFAULT 0x00400000U 
/* register array ndp120.dsp_config.bwcoef_b0_cfg[4] */
#define NDP120_DSP_CONFIG_BWCOEF_B0_CFG(i) (0x4000c040U + ((i) << 2))
#define NDP120_DSP_CONFIG_BWCOEF_B0_CFG_COUNT 4
#define NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_SHIFT 0
#define NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_MASK 0x00ffffffU
#define NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0(v) \
        ((v) << NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_MASK) | ((v) << NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_MASK) >> NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_B0_CFG_BWCOEF_B0_DEFAULT 0x0038c2ecU
#define NDP120_DSP_CONFIG_BWCOEF_B0_CFG_DEFAULT 0x0038c2ecU 
/* register array ndp120.dsp_config.bwcoef_a1_cfg[4] */
#define NDP120_DSP_CONFIG_BWCOEF_A1_CFG(i) (0x4000c050U + ((i) << 2))
#define NDP120_DSP_CONFIG_BWCOEF_A1_CFG_COUNT 4
#define NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_SHIFT 0
#define NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_MASK 0x00ffffffU
#define NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1(v) \
        ((v) << NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_MASK) | ((v) << NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_MASK) >> NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_A1_CFG_BWCOEF_A1_DEFAULT 0x0080a0c7U
#define NDP120_DSP_CONFIG_BWCOEF_A1_CFG_DEFAULT 0x0080a0c7U 
/* register array ndp120.dsp_config.bwcoef_b1_cfg[4] */
#define NDP120_DSP_CONFIG_BWCOEF_B1_CFG(i) (0x4000c060U + ((i) << 2))
#define NDP120_DSP_CONFIG_BWCOEF_B1_CFG_COUNT 4
#define NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_SHIFT 0
#define NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_MASK 0x00ffffffU
#define NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1(v) \
        ((v) << NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_MASK) | ((v) << NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_MASK) >> NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_B1_CFG_BWCOEF_B1_DEFAULT 0x008e7a26U
#define NDP120_DSP_CONFIG_BWCOEF_B1_CFG_DEFAULT 0x008e7a26U 
/* register array ndp120.dsp_config.bwcoef_a2_cfg[4] */
#define NDP120_DSP_CONFIG_BWCOEF_A2_CFG(i) (0x4000c070U + ((i) << 2))
#define NDP120_DSP_CONFIG_BWCOEF_A2_CFG_COUNT 4
#define NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_SHIFT 0
#define NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_MASK 0x00ffffffU
#define NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2(v) \
        ((v) << NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_MASK) | ((v) << NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_MASK) >> NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_A2_CFG_BWCOEF_A2_DEFAULT 0x003f60a5U
#define NDP120_DSP_CONFIG_BWCOEF_A2_CFG_DEFAULT 0x003f60a5U 
/* register array ndp120.dsp_config.bwcoef_b2_cfg[4] */
#define NDP120_DSP_CONFIG_BWCOEF_B2_CFG(i) (0x4000c080U + ((i) << 2))
#define NDP120_DSP_CONFIG_BWCOEF_B2_CFG_COUNT 4
#define NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_SHIFT 0
#define NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_MASK 0x00ffffffU
#define NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2(v) \
        ((v) << NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_MASK) | ((v) << NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_SHIFT))
#define NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_MASK) >> NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_SHIFT)
#define NDP120_DSP_CONFIG_BWCOEF_B2_CFG_BWCOEF_B2_DEFAULT 0x0038c2ecU
#define NDP120_DSP_CONFIG_BWCOEF_B2_CFG_DEFAULT 0x0038c2ecU 
/* register array ndp120.dsp_config.farrowcfg[3] */
#define NDP120_DSP_CONFIG_FARROWCFG(i) (0x4000c090U + ((i) << 2))
#define NDP120_DSP_CONFIG_FARROWCFG_COUNT 3
#define NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_SHIFT 0
#define NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_MASK 0x0fffffffU
#define NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP(v) \
        ((v) << NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_SHIFT)
#define NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_SHIFT))
#define NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_MASK) | ((v) << NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_SHIFT))
#define NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_MASK) >> NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_SHIFT)
#define NDP120_DSP_CONFIG_FARROWCFG_FRPHASESTEP_DEFAULT 0x08000000U
#define NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_SHIFT 28
#define NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_MASK 0x10000000U
#define NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW(v) \
        ((v) << NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_SHIFT)
#define NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_SHIFT))
#define NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_MASK) | ((v) << NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_SHIFT))
#define NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_MASK) >> NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_SHIFT)
#define NDP120_DSP_CONFIG_FARROWCFG_BYPASS_FARROW_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_FARROWCFG_DEFAULT 0x08000000U 
/* register array ndp120.dsp_config.misccfg[6] */
#define NDP120_DSP_CONFIG_MISCCFG(i) (0x4000c09cU + ((i) << 2))
#define NDP120_DSP_CONFIG_MISCCFG_COUNT 6
#define NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_SHIFT 0
#define NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_MASK 0x0000003fU
#define NDP120_DSP_CONFIG_MISCCFG_NUMDELAY(v) \
        ((v) << NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_SHIFT)
#define NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_SHIFT))
#define NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_MASK) | ((v) << NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_SHIFT))
#define NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_MASK) >> NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_SHIFT)
#define NDP120_DSP_CONFIG_MISCCFG_NUMDELAY_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_SHIFT 6
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_MASK 0x00000040U
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR(v) \
        ((v) << NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_SHIFT)
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_SHIFT))
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_MASK) | ((v) << NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_SHIFT))
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_MASK) >> NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_SHIFT)
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTDIR_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_SHIFT 7
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_MASK 0x00000380U
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT(v) \
        ((v) << NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_SHIFT)
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_SHIFT))
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_MASK) | ((v) << NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_SHIFT))
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_MASK) >> NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_SHIFT)
#define NDP120_DSP_CONFIG_MISCCFG_AGCSHIFTCNT_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_SHIFT 10
#define NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_MASK 0x00fffc00U
#define NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL(v) \
        ((v) << NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_SHIFT)
#define NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_SHIFT))
#define NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_MASK) | ((v) << NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_SHIFT))
#define NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_MASK) >> NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_SHIFT)
#define NDP120_DSP_CONFIG_MISCCFG_AGCFINEGRAINMUL_DEFAULT 0x00002000U
#define NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_SHIFT 24
#define NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_MASK 0x01000000U
#define NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE(v) \
        ((v) << NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_SHIFT)
#define NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_SHIFT))
#define NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_MASK) | ((v) << NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_SHIFT))
#define NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_MASK) >> NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_SHIFT)
#define NDP120_DSP_CONFIG_MISCCFG_ZCGAINCHANGEENABLE_DEFAULT 0x00000001U
#define NDP120_DSP_CONFIG_MISCCFG_DEFAULT 0x01800000U 
/* register array ndp120.dsp_config.tdmchnctl[4] */
#define NDP120_DSP_CONFIG_TDMCHNCTL(i) (0x4000c0b4U + ((i) << 2))
#define NDP120_DSP_CONFIG_TDMCHNCTL_COUNT 4
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_SHIFT 0
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_MASK 0x0000000fU
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT(v) \
        ((v) << NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_SHIFT)
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_SHIFT))
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_MASK) | ((v) << NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_SHIFT))
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_MASK) >> NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_SHIFT)
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLCNT_DEFAULT 0x00000004U
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_SHIFT 4
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_MASK 0x000000f0U
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL(v) \
        ((v) << NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_SHIFT)
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_SHIFT))
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_MASK) | ((v) << NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_SHIFT))
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_MASK) >> NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_SHIFT)
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLLEFTSEL_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_SHIFT 8
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_MASK 0x00000f00U
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL(v) \
        ((v) << NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_SHIFT)
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_SHIFT))
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_MASK) | ((v) << NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_SHIFT))
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_MASK) >> NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_SHIFT)
#define NDP120_DSP_CONFIG_TDMCHNCTL_TDMCHNLRIGHTSEL_DEFAULT 0x00000001U
#define NDP120_DSP_CONFIG_TDMCHNCTL_DEFAULT 0x00000104U 
/* register array ndp120.dsp_config.fifosamplethreshold[5] */
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD(i) (0x4000c0c4U + ((i) << 2))
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_COUNT 5
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_SHIFT 0
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_MASK 0x0000000fU
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD(v) \
        ((v) << NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_MASK) | ((v) << NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_MASK) >> NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_THRESHOLD_DEFAULT 0x00000004U
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL_SHIFT 4
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL_MASK 0x000001f0U
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL(v) \
        ((v) << NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL_SHIFT)
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL_SHIFT))
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL_MASK) | ((v) << NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL_SHIFT))
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL_MASK) >> NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_FILL_LEVEL_SHIFT)
#define NDP120_DSP_CONFIG_FIFOSAMPLETHRESHOLD_DEFAULT 0x00000004U 
/* register ndp120.dsp_config.fifoctrl */
#define NDP120_DSP_CONFIG_FIFOCTRL 0x4000c0d8U
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_SHIFT 0
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_MASK 0x00000007U
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL(v) \
        ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_MASK) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_MASK) >> NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_VAL_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_SHIFT 3
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_MASK 0x00000038U
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN(v) \
        ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_MASK) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_MASK) >> NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_SEL_OVRD_EN_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_SHIFT 6
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_MASK 0x000000c0U
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL(v) \
        ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_MASK) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_MASK) >> NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_FIFO_IRQ_CTL_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD_SHIFT 8
#define NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD_MASK 0x00001f00U
#define NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD(v) \
        ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD_MASK) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD_MASK) >> NDP120_DSP_CONFIG_FIFOCTRL_FILL_LEVEL_ABOVE_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_SHIFT 13
#define NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_MASK 0x0003e000U
#define NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR(v) \
        ((v) << NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_MASK) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_MASK) >> NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_RESET_FIFO_PTR_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_SHIFT 18
#define NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_MASK 0x00040000U
#define NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB(v) \
        ((v) << NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_MASK) | ((v) << NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_SHIFT))
#define NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_MASK) >> NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_SHIFT)
#define NDP120_DSP_CONFIG_FIFOCTRL_AUDIO_FIFO_RSTB_DEFAULT 0x00000001U
#define NDP120_DSP_CONFIG_FIFOCTRL_DEFAULT 0x00040000U 
/* register ndp120.dsp_config.audiosamplethreshold */
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD 0x4000c0dcU
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_SHIFT 0
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_MASK 0x000000ffU
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD(v) \
        ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_MASK) | ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_MASK) >> NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_THRESHOLD_DEFAULT 0x00000020U
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_SHIFT 8
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_MASK 0x0000ff00U
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD(v) \
        ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_MASK) | ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_MASK) >> NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_SPACE_THRESHOLD_DEFAULT 0x00000020U
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_SHIFT 16
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_MASK 0x00010000U
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS(v) \
        ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_SHIFT)
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_SHIFT))
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_MASK) | ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_SHIFT))
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_MASK) >> NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_SHIFT)
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_LATCH_COUNTERS_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL_SHIFT 17
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL_MASK 0x03fe0000U
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL(v) \
        ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL_SHIFT)
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL_SHIFT))
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL_MASK) | ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL_SHIFT))
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL_MASK) >> NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_AUDIO_SAMPLE_FILL_LEVEL_SHIFT)
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_SHIFT 26
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_MASK 0x04000000U
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR(v) \
        ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_SHIFT)
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_SHIFT))
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_MASK) | ((v) << NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_SHIFT))
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_MASK) >> NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_SHIFT)
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_RESET_FIFO_PTR_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_AUDIOSAMPLETHRESHOLD_DEFAULT 0x00002020U 
/* register ndp120.dsp_config.indomaincntr */
#define NDP120_DSP_CONFIG_INDOMAINCNTR 0x4000c0e0U
#define NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR_SHIFT 0
#define NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR_MASK 0xffffffffU
#define NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR(v) \
        ((v) << NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR_SHIFT)
#define NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR_SHIFT))
#define NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR_MASK) | ((v) << NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR_SHIFT))
#define NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR_MASK) >> NDP120_DSP_CONFIG_INDOMAINCNTR_INDOMAINCNTR_SHIFT)
/* register ndp120.dsp_config.outdomaincntr */
#define NDP120_DSP_CONFIG_OUTDOMAINCNTR 0x4000c0e4U
#define NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR_SHIFT 0
#define NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR_MASK 0xffffffffU
#define NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR(v) \
        ((v) << NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR_SHIFT)
#define NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR_SHIFT))
#define NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR_MASK) | ((v) << NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR_SHIFT))
#define NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR_MASK) >> NDP120_DSP_CONFIG_OUTDOMAINCNTR_OUTDOMAINCNTR_SHIFT)
/* register array ndp120.dsp_config.bufstartaddr[5] */
#define NDP120_DSP_CONFIG_BUFSTARTADDR(i) (0x4000c0e8U + ((i) << 2))
#define NDP120_DSP_CONFIG_BUFSTARTADDR_COUNT 5
#define NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_SHIFT 0
#define NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_MASK 0xffffffffU
#define NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR(v) \
        ((v) << NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_SHIFT)
#define NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_SHIFT))
#define NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_MASK) | ((v) << NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_SHIFT))
#define NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_MASK) >> NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_SHIFT)
#define NDP120_DSP_CONFIG_BUFSTARTADDR_BUF_START_ADDR_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_BUFSTARTADDR_DEFAULT 0x00000000U 
/* register array ndp120.dsp_config.bufendaddr[5] */
#define NDP120_DSP_CONFIG_BUFENDADDR(i) (0x4000c0fcU + ((i) << 2))
#define NDP120_DSP_CONFIG_BUFENDADDR_COUNT 5
#define NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_SHIFT 0
#define NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_MASK 0xffffffffU
#define NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR(v) \
        ((v) << NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_SHIFT)
#define NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_SHIFT))
#define NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_MASK) | ((v) << NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_SHIFT))
#define NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_MASK) >> NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_SHIFT)
#define NDP120_DSP_CONFIG_BUFENDADDR_BUF_END_ADDR_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_BUFENDADDR_DEFAULT 0x00000000U 
/* register array ndp120.dsp_config.bufctrl[5] */
#define NDP120_DSP_CONFIG_BUFCTRL(i) (0x4000c110U + ((i) << 2))
#define NDP120_DSP_CONFIG_BUFCTRL_COUNT 5
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_SHIFT 0
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_MASK 0x0000ffffU
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD(v) \
        ((v) << NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_MASK) | ((v) << NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_MASK) >> NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_FILL_THRESHOLD_DEFAULT 0x000000a0U
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_SHIFT 16
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_MASK 0x00030000U
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE(v) \
        ((v) << NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_SHIFT)
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_SHIFT))
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_MASK) | ((v) << NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_SHIFT))
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_MASK) >> NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_SHIFT)
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_BURST1 0x0U
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_BURST4 0x1U
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_BURST8 0x2U
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_BURST16 0x3U
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_MAX 0x3U
#define NDP120_DSP_CONFIG_BUFCTRL_BUF_MAX_BURST_SIZE_VALID(v) \
        (v >= 0 && v <= 3)
#define NDP120_DSP_CONFIG_BUFCTRL_DEFAULT 0x000000a0U 
/* register array ndp120.dsp_config.bufcurwrptr[5] */
#define NDP120_DSP_CONFIG_BUFCURWRPTR(i) (0x4000c124U + ((i) << 2))
#define NDP120_DSP_CONFIG_BUFCURWRPTR_COUNT 5
#define NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR_SHIFT 0
#define NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR_MASK 0xffffffffU
#define NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR(v) \
        ((v) << NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR_SHIFT)
#define NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR_SHIFT))
#define NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR_MASK) | ((v) << NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR_SHIFT))
#define NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR_MASK) >> NDP120_DSP_CONFIG_BUFCURWRPTR_BUF_CUR_WR_PTR_SHIFT)
/* register array ndp120.dsp_config.bufblockwrptr[5] */
#define NDP120_DSP_CONFIG_BUFBLOCKWRPTR(i) (0x4000c138U + ((i) << 2))
#define NDP120_DSP_CONFIG_BUFBLOCKWRPTR_COUNT 5
#define NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR_SHIFT 0
#define NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR_MASK 0xffffffffU
#define NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR(v) \
        ((v) << NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR_SHIFT)
#define NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR_SHIFT))
#define NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR_MASK) | ((v) << NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR_SHIFT))
#define NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR_MASK) >> NDP120_DSP_CONFIG_BUFBLOCKWRPTR_BUF_BLOCK_WR_PTR_SHIFT)
/* register array ndp120.dsp_config.buffilllevel[5] */
#define NDP120_DSP_CONFIG_BUFFILLLEVEL(i) (0x4000c14cU + ((i) << 2))
#define NDP120_DSP_CONFIG_BUFFILLLEVEL_COUNT 5
#define NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL_SHIFT 0
#define NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL_MASK 0x0000ffffU
#define NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL(v) \
        ((v) << NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL_SHIFT)
#define NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL_SHIFT))
#define NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL_MASK) | ((v) << NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL_SHIFT))
#define NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL_MASK) >> NDP120_DSP_CONFIG_BUFFILLLEVEL_BUF_FILL_LEVEL_SHIFT)
/* register ndp120.dsp_config.bufirqstat */
#define NDP120_DSP_CONFIG_BUFIRQSTAT 0x4000c160U
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD_SHIFT 0
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD_MASK 0x0000001fU
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD(v) \
        ((v) << NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD_MASK) | ((v) << NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD_MASK) >> NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_FILL_ABOVE_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR_SHIFT 5
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR_MASK 0x000003e0U
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR(v) \
        ((v) << NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR_SHIFT)
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR_SHIFT))
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR_MASK) | ((v) << NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR_SHIFT))
#define NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR_MASK) >> NDP120_DSP_CONFIG_BUFIRQSTAT_STAT_BUF_ERR_SHIFT)
/* register ndp120.dsp_config.bufclrirqstat */
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT 0x4000c164U
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_SHIFT 0
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_MASK 0x0000001fU
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD(v) \
        ((v) << NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_MASK) | ((v) << NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_SHIFT))
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_MASK) >> NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_SHIFT)
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_FILL_ABOVE_THRESHOLD_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_SHIFT 5
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_MASK 0x000003e0U
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR(v) \
        ((v) << NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_SHIFT)
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_SHIFT))
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_MASK) | ((v) << NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_SHIFT))
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_MASK) >> NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_SHIFT)
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_CLR_STAT_BUF_ERR_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_BUFCLRIRQSTAT_DEFAULT 0x00000000U 
/* register ndp120.dsp_config.aud2_regfile_settings */
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS 0x4000c168U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_SHIFT 0
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_MASK 0x00000007U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA(v) \
        ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_MASK) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_MASK) >> NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMA_DEFAULT 0x00000004U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_SHIFT 3
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_MASK 0x00000018U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW(v) \
        ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_MASK) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_MASK) >> NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_EMAW_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_SHIFT 5
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_MASK 0x00000020U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL(v) \
        ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_MASK) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_MASK) >> NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWL_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_SHIFT 6
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_MASK 0x00000040U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL(v) \
        ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_MASK) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_MASK) >> NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABL_DEFAULT 0x00000001U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_SHIFT 7
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_MASK 0x00000180U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM(v) \
        ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_MASK) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_MASK) >> NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RAWLM_DEFAULT 0x00000000U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_SHIFT 9
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_MASK 0x00000600U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM(v) \
        ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_MASK) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_MASK) >> NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_WABLM_DEFAULT 0x00000003U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_SHIFT 11
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_MASK 0x00000800U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N(v) \
        ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_MASK) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_MASK) >> NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET1N_DEFAULT 0x00000001U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_SHIFT 12
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_MASK 0x00001000U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N(v) \
        ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_MASK) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_MASK) >> NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_RET2N_DEFAULT 0x00000001U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_SHIFT 13
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_MASK 0x00002000U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN(v) \
        ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_MASK) | ((v) << NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_SHIFT))
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_EXTRACT(x) \
        (((x) & NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_MASK) >> NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_SHIFT)
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_PGEN_DEFAULT 0x00000001U
#define NDP120_DSP_CONFIG_AUD2_REGFILE_SETTINGS_DEFAULT 0x00003e44U 

/*
 * block ndp120.dnn_config, base 0x4000d000
 */
#define NDP120_DNN_CONFIG 0x4000d000U
#define NDP120_DNN_CONFIG_SIZE 0x00001000U
/* register ndp120.dnn_config.id */
#define NDP120_DNN_CONFIG_ID 0x4000d000U
/* register ndp120.dnn_config.dnncfg */
#define NDP120_DNN_CONFIG_DNNCFG 0x4000d004U
#define NDP120_DNN_CONFIG_DNNCFG_RSTB_SHIFT 0
#define NDP120_DNN_CONFIG_DNNCFG_RSTB_MASK 0x00000001U
#define NDP120_DNN_CONFIG_DNNCFG_RSTB(v) \
        ((v) << NDP120_DNN_CONFIG_DNNCFG_RSTB_SHIFT)
#define NDP120_DNN_CONFIG_DNNCFG_RSTB_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNCFG_RSTB_SHIFT))
#define NDP120_DNN_CONFIG_DNNCFG_RSTB_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNCFG_RSTB_MASK) | ((v) << NDP120_DNN_CONFIG_DNNCFG_RSTB_SHIFT))
#define NDP120_DNN_CONFIG_DNNCFG_RSTB_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNCFG_RSTB_MASK) >> NDP120_DNN_CONFIG_DNNCFG_RSTB_SHIFT)
#define NDP120_DNN_CONFIG_DNNCFG_RSTB_DEFAULT 0x00000001U
#define NDP120_DNN_CONFIG_DNNCFG_ENABLE_SHIFT 1
#define NDP120_DNN_CONFIG_DNNCFG_ENABLE_MASK 0x00000002U
#define NDP120_DNN_CONFIG_DNNCFG_ENABLE(v) \
        ((v) << NDP120_DNN_CONFIG_DNNCFG_ENABLE_SHIFT)
#define NDP120_DNN_CONFIG_DNNCFG_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNCFG_ENABLE_SHIFT))
#define NDP120_DNN_CONFIG_DNNCFG_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNCFG_ENABLE_MASK) | ((v) << NDP120_DNN_CONFIG_DNNCFG_ENABLE_SHIFT))
#define NDP120_DNN_CONFIG_DNNCFG_ENABLE_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNCFG_ENABLE_MASK) >> NDP120_DNN_CONFIG_DNNCFG_ENABLE_SHIFT)
#define NDP120_DNN_CONFIG_DNNCFG_ENABLE_DEFAULT 0x00000000U
#define NDP120_DNN_CONFIG_DNNCFG_RET_MODE_SHIFT 2
#define NDP120_DNN_CONFIG_DNNCFG_RET_MODE_MASK 0x00000004U
#define NDP120_DNN_CONFIG_DNNCFG_RET_MODE(v) \
        ((v) << NDP120_DNN_CONFIG_DNNCFG_RET_MODE_SHIFT)
#define NDP120_DNN_CONFIG_DNNCFG_RET_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNCFG_RET_MODE_SHIFT))
#define NDP120_DNN_CONFIG_DNNCFG_RET_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNCFG_RET_MODE_MASK) | ((v) << NDP120_DNN_CONFIG_DNNCFG_RET_MODE_SHIFT))
#define NDP120_DNN_CONFIG_DNNCFG_RET_MODE_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNCFG_RET_MODE_MASK) >> NDP120_DNN_CONFIG_DNNCFG_RET_MODE_SHIFT)
#define NDP120_DNN_CONFIG_DNNCFG_RET_MODE_DEFAULT 0x00000000U
#define NDP120_DNN_CONFIG_DNNCFG_RET_MODE_RET_MOD2 0x0U
#define NDP120_DNN_CONFIG_DNNCFG_RET_MODE_RET_MOD1 0x1U
#define NDP120_DNN_CONFIG_DNNCFG_RET_MODE_MAX 0x1U
#define NDP120_DNN_CONFIG_DNNCFG_RET_MODE_VALID(v) \
        (v >= 0 && v <= 1)
#define NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_SHIFT 3
#define NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_MASK 0x000000f8U
#define NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE(v) \
        ((v) << NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_SHIFT)
#define NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_SHIFT))
#define NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_MASK) | ((v) << NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_SHIFT))
#define NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_MASK) >> NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_SHIFT)
#define NDP120_DNN_CONFIG_DNNCFG_RET_WAKE_CYCLE_DEFAULT 0x00000005U
#define NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_SHIFT 8
#define NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_MASK 0x007fff00U
#define NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET(v) \
        ((v) << NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_SHIFT)
#define NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_SHIFT))
#define NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_MASK) | ((v) << NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_SHIFT))
#define NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_MASK) >> NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_SHIFT)
#define NDP120_DNN_CONFIG_DNNCFG_INSTRUCTION_OFFSET_DEFAULT 0x00000000U
#define NDP120_DNN_CONFIG_DNNCFG_DEFAULT 0x00000029U 
/* register ndp120.dnn_config.dnnintcfg */
#define NDP120_DNN_CONFIG_DNNINTCFG 0x4000d008U
#define NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_SHIFT 0
#define NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_MASK 0x000000ffU
#define NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK(v) \
        ((v) << NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_SHIFT)
#define NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_SHIFT))
#define NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_MASK) | ((v) << NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_SHIFT))
#define NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_MASK) >> NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_SHIFT)
#define NDP120_DNN_CONFIG_DNNINTCFG_LAYER_MASK_DEFAULT 0x00000000U
#define NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_SHIFT 8
#define NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_MASK 0x00000100U
#define NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK(v) \
        ((v) << NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_SHIFT)
#define NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_SHIFT))
#define NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_MASK) | ((v) << NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_SHIFT))
#define NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_MASK) >> NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_SHIFT)
#define NDP120_DNN_CONFIG_DNNINTCFG_ERROR_MASK_DEFAULT 0x00000000U
#define NDP120_DNN_CONFIG_DNNINTCFG_DEFAULT 0x00000000U 
/* register ndp120.dnn_config.dnnctl */
#define NDP120_DNN_CONFIG_DNNCTL 0x4000d00cU
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_SHIFT 0
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_MASK 0x00000001U
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER(v) \
        ((v) << NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_SHIFT)
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_SHIFT))
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_MASK) | ((v) << NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_SHIFT))
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_MASK) >> NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_SHIFT)
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_DEFAULT 0x00000000U
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_SHIFT 1
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_MASK 0x000001feU
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX(v) \
        ((v) << NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_SHIFT)
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_SHIFT))
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_MASK) | ((v) << NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_SHIFT))
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_MASK) >> NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_SHIFT)
#define NDP120_DNN_CONFIG_DNNCTL_RUN_LAYER_INDEX_DEFAULT 0x00000000U
#define NDP120_DNN_CONFIG_DNNCTL_DEFAULT 0x00000000U 
/* register ndp120.dnn_config.dnnintsts */
#define NDP120_DNN_CONFIG_DNNINTSTS 0x4000d010U
#define NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS_SHIFT 0
#define NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS_MASK 0x000000ffU
#define NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS(v) \
        ((v) << NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS_SHIFT)
#define NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS_SHIFT))
#define NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS_MASK) | ((v) << NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS_SHIFT))
#define NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS_MASK) >> NDP120_DNN_CONFIG_DNNINTSTS_LAYER_STATUS_SHIFT)
#define NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS_SHIFT 8
#define NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS_MASK 0x00000100U
#define NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS(v) \
        ((v) << NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS_SHIFT)
#define NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS_SHIFT))
#define NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS_MASK) | ((v) << NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS_SHIFT))
#define NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS_MASK) >> NDP120_DNN_CONFIG_DNNINTSTS_ERROR_STATUS_SHIFT)
/* register ndp120.dnn_config.dnnsts0 */
#define NDP120_DNN_CONFIG_DNNSTS0 0x4000d014U
#define NDP120_DNN_CONFIG_DNNSTS0_RUNNING_SHIFT 0
#define NDP120_DNN_CONFIG_DNNSTS0_RUNNING_MASK 0x00000001U
#define NDP120_DNN_CONFIG_DNNSTS0_RUNNING(v) \
        ((v) << NDP120_DNN_CONFIG_DNNSTS0_RUNNING_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS0_RUNNING_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNSTS0_RUNNING_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS0_RUNNING_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNSTS0_RUNNING_MASK) | ((v) << NDP120_DNN_CONFIG_DNNSTS0_RUNNING_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS0_RUNNING_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNSTS0_RUNNING_MASK) >> NDP120_DNN_CONFIG_DNNSTS0_RUNNING_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS0_RUNNING_IDLE 0x0U
#define NDP120_DNN_CONFIG_DNNSTS0_RUNNING_RUNNING 0x1U
#define NDP120_DNN_CONFIG_DNNSTS0_RUNNING_MAX 0x1U
#define NDP120_DNN_CONFIG_DNNSTS0_RUNNING_VALID(v) \
        (v >= 0 && v <= 1)
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_START_SHIFT 1
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_START_MASK 0x00000002U
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_START(v) \
        ((v) << NDP120_DNN_CONFIG_DNNSTS0_LAYER_START_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_START_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNSTS0_LAYER_START_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_START_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNSTS0_LAYER_START_MASK) | ((v) << NDP120_DNN_CONFIG_DNNSTS0_LAYER_START_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_START_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNSTS0_LAYER_START_MASK) >> NDP120_DNN_CONFIG_DNNSTS0_LAYER_START_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE_SHIFT 2
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE_MASK 0x00000004U
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE(v) \
        ((v) << NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE_MASK) | ((v) << NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE_MASK) >> NDP120_DNN_CONFIG_DNNSTS0_LAYER_DONE_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_SHIFT 3
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_MASK 0x00000078U
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE(v) \
        ((v) << NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_MASK) | ((v) << NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_MASK) >> NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_NO_ERROR 0x0U
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_OFFSET 0x1U
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_MEM_RANGE 0x2U
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_TYPE 0x3U
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_ZERO_SIZE 0x4U
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_MAX 0x4U
#define NDP120_DNN_CONFIG_DNNSTS0_ERROR_CODE_VALID(v) \
        (v >= 0 && v <= 4)
/* register ndp120.dnn_config.dnnsts1 */
#define NDP120_DNN_CONFIG_DNNSTS1 0x4000d018U
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX_SHIFT 0
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX_MASK 0x000000ffU
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX(v) \
        ((v) << NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX_MASK) | ((v) << NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX_MASK) >> NDP120_DNN_CONFIG_DNNSTS1_LAYER_INDEX_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX_SHIFT 8
#define NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX_MASK 0x0000ff00U
#define NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX(v) \
        ((v) << NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX_MASK) | ((v) << NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX_MASK) >> NDP120_DNN_CONFIG_DNNSTS1_START_LAYER_INDEX_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT_SHIFT 16
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT_MASK 0x00ff0000U
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT(v) \
        ((v) << NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT_MASK) | ((v) << NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT_MASK) >> NDP120_DNN_CONFIG_DNNSTS1_LAYER_COUNT_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT_SHIFT 24
#define NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT_MASK 0xff000000U
#define NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT(v) \
        ((v) << NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT_MASK) | ((v) << NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT_MASK) >> NDP120_DNN_CONFIG_DNNSTS1_FRAME_COUNT_SHIFT)
/* register ndp120.dnn_config.dnnsts2 */
#define NDP120_DNN_CONFIG_DNNSTS2 0x4000d01cU
#define NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR_SHIFT 0
#define NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR_MASK 0xffffffffU
#define NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR(v) \
        ((v) << NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR_MASK) | ((v) << NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR_MASK) >> NDP120_DNN_CONFIG_DNNSTS2_INPUT_BASE_ADDR_SHIFT)
/* register ndp120.dnn_config.dnnsts3 */
#define NDP120_DNN_CONFIG_DNNSTS3 0x4000d020U
#define NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR_SHIFT 0
#define NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR_MASK 0xffffffffU
#define NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR(v) \
        ((v) << NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR_SHIFT)
#define NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR_MASK) | ((v) << NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR_SHIFT))
#define NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR_MASK) >> NDP120_DNN_CONFIG_DNNSTS3_OUTPUT_BASE_ADDR_SHIFT)
/* register ndp120.dnn_config.dnnmemcfg */
#define NDP120_DNN_CONFIG_DNNMEMCFG 0x4000d024U
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMA_SHIFT 0
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMA_MASK 0x00000007U
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMA(v) \
        ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_EMA_SHIFT)
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMA_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_EMA_SHIFT))
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMA_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNMEMCFG_EMA_MASK) | ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_EMA_SHIFT))
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMA_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNMEMCFG_EMA_MASK) >> NDP120_DNN_CONFIG_DNNMEMCFG_EMA_SHIFT)
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMA_DEFAULT 0x00000007U
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_SHIFT 3
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_MASK 0x00000018U
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMAW(v) \
        ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_SHIFT)
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_SHIFT))
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_MASK) | ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_SHIFT))
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_MASK) >> NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_SHIFT)
#define NDP120_DNN_CONFIG_DNNMEMCFG_EMAW_DEFAULT 0x00000000U
#define NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_SHIFT 5
#define NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_MASK 0x000000e0U
#define NDP120_DNN_CONFIG_DNNMEMCFG_RAWL(v) \
        ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_SHIFT)
#define NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_SHIFT))
#define NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_MASK) | ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_SHIFT))
#define NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_MASK) >> NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_SHIFT)
#define NDP120_DNN_CONFIG_DNNMEMCFG_RAWL_DEFAULT 0x00000000U
#define NDP120_DNN_CONFIG_DNNMEMCFG_WABL_SHIFT 8
#define NDP120_DNN_CONFIG_DNNMEMCFG_WABL_MASK 0x00000700U
#define NDP120_DNN_CONFIG_DNNMEMCFG_WABL(v) \
        ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_WABL_SHIFT)
#define NDP120_DNN_CONFIG_DNNMEMCFG_WABL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_WABL_SHIFT))
#define NDP120_DNN_CONFIG_DNNMEMCFG_WABL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNMEMCFG_WABL_MASK) | ((v) << NDP120_DNN_CONFIG_DNNMEMCFG_WABL_SHIFT))
#define NDP120_DNN_CONFIG_DNNMEMCFG_WABL_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNMEMCFG_WABL_MASK) >> NDP120_DNN_CONFIG_DNNMEMCFG_WABL_SHIFT)
#define NDP120_DNN_CONFIG_DNNMEMCFG_WABL_DEFAULT 0x00000007U
#define NDP120_DNN_CONFIG_DNNMEMCFG_DEFAULT 0x00000707U 
/* register ndp120.dnn_config.dnndatacfg0 */
#define NDP120_DNN_CONFIG_DNNDATACFG0 0x4000d028U
#define NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_SHIFT 0
#define NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_MASK 0x0000ffffU
#define NDP120_DNN_CONFIG_DNNDATACFG0_PGEN(v) \
        ((v) << NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_SHIFT)
#define NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_SHIFT))
#define NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_MASK) | ((v) << NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_SHIFT))
#define NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_MASK) >> NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_SHIFT)
#define NDP120_DNN_CONFIG_DNNDATACFG0_PGEN_DEFAULT 0x0000ffffU
#define NDP120_DNN_CONFIG_DNNDATACFG0_DEFAULT 0x0000ffffU 
/* register ndp120.dnn_config.dnndatacfg1 */
#define NDP120_DNN_CONFIG_DNNDATACFG1 0x4000d02cU
#define NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_SHIFT 0
#define NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_MASK 0x0000ffffU
#define NDP120_DNN_CONFIG_DNNDATACFG1_RET1N(v) \
        ((v) << NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_SHIFT)
#define NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_SHIFT))
#define NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_MASK) | ((v) << NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_SHIFT))
#define NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_MASK) >> NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_SHIFT)
#define NDP120_DNN_CONFIG_DNNDATACFG1_RET1N_DEFAULT 0x0000ffffU
#define NDP120_DNN_CONFIG_DNNDATACFG1_DEFAULT 0x0000ffffU 
/* register ndp120.dnn_config.dnndatacfg2 */
#define NDP120_DNN_CONFIG_DNNDATACFG2 0x4000d030U
#define NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_SHIFT 0
#define NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_MASK 0x0000ffffU
#define NDP120_DNN_CONFIG_DNNDATACFG2_RET2N(v) \
        ((v) << NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_SHIFT)
#define NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_SHIFT))
#define NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_MASK) | ((v) << NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_SHIFT))
#define NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_MASK) >> NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_SHIFT)
#define NDP120_DNN_CONFIG_DNNDATACFG2_RET2N_DEFAULT 0x0000ffffU
#define NDP120_DNN_CONFIG_DNNDATACFG2_DEFAULT 0x0000ffffU 
/* register ndp120.dnn_config.dnndatacfg3 */
#define NDP120_DNN_CONFIG_DNNDATACFG3 0x4000d034U
#define NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_SHIFT 0
#define NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_MASK 0x0000ffffU
#define NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE(v) \
        ((v) << NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_SHIFT)
#define NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_SHIFT))
#define NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_MASK) | ((v) << NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_SHIFT))
#define NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_MASK) >> NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_SHIFT)
#define NDP120_DNN_CONFIG_DNNDATACFG3_RET_OVERRIDE_DEFAULT 0x00000000U
#define NDP120_DNN_CONFIG_DNNDATACFG3_DEFAULT 0x00000000U 
/* register ndp120.dnn_config.dnndatasts */
#define NDP120_DNN_CONFIG_DNNDATASTS 0x4000d038U
#define NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL_SHIFT 0
#define NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL_MASK 0x0000ffffU
#define NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL(v) \
        ((v) << NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL_SHIFT)
#define NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL_SHIFT))
#define NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL_MASK) | ((v) << NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL_SHIFT))
#define NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL_MASK) >> NDP120_DNN_CONFIG_DNNDATASTS_RETN_CNTRL_SHIFT)
/* register ndp120.dnn_config.dnnparamscfg0 */
#define NDP120_DNN_CONFIG_DNNPARAMSCFG0 0x4000d03cU
#define NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_SHIFT 0
#define NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_MASK 0x000fffffU
#define NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN(v) \
        ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_SHIFT)
#define NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_SHIFT))
#define NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_MASK) | ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_SHIFT))
#define NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_MASK) >> NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_SHIFT)
#define NDP120_DNN_CONFIG_DNNPARAMSCFG0_PGEN_DEFAULT 0x000fffffU
#define NDP120_DNN_CONFIG_DNNPARAMSCFG0_DEFAULT 0x000fffffU 
/* register ndp120.dnn_config.dnnparamscfg1 */
#define NDP120_DNN_CONFIG_DNNPARAMSCFG1 0x4000d040U
#define NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_SHIFT 0
#define NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_MASK 0x000fffffU
#define NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N(v) \
        ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_SHIFT)
#define NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_SHIFT))
#define NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_MASK) | ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_SHIFT))
#define NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_MASK) >> NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_SHIFT)
#define NDP120_DNN_CONFIG_DNNPARAMSCFG1_RET1N_DEFAULT 0x000fffffU
#define NDP120_DNN_CONFIG_DNNPARAMSCFG1_DEFAULT 0x000fffffU 
/* register ndp120.dnn_config.dnnparamscfg2 */
#define NDP120_DNN_CONFIG_DNNPARAMSCFG2 0x4000d044U
#define NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_SHIFT 0
#define NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_MASK 0x000fffffU
#define NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N(v) \
        ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_SHIFT)
#define NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_SHIFT))
#define NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_MASK) | ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_SHIFT))
#define NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_MASK) >> NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_SHIFT)
#define NDP120_DNN_CONFIG_DNNPARAMSCFG2_RET2N_DEFAULT 0x000fffffU
#define NDP120_DNN_CONFIG_DNNPARAMSCFG2_DEFAULT 0x000fffffU 
/* register ndp120.dnn_config.dnnparamscfg3 */
#define NDP120_DNN_CONFIG_DNNPARAMSCFG3 0x4000d048U
#define NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_SHIFT 0
#define NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_MASK 0x000fffffU
#define NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE(v) \
        ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_SHIFT)
#define NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_SHIFT))
#define NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_MASK) | ((v) << NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_SHIFT))
#define NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_MASK) >> NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_SHIFT)
#define NDP120_DNN_CONFIG_DNNPARAMSCFG3_RET_OVERRIDE_DEFAULT 0x00000000U
#define NDP120_DNN_CONFIG_DNNPARAMSCFG3_DEFAULT 0x00000000U 
/* register ndp120.dnn_config.dnnparamssts */
#define NDP120_DNN_CONFIG_DNNPARAMSSTS 0x4000d04cU
#define NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL_SHIFT 0
#define NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL_MASK 0x000fffffU
#define NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL(v) \
        ((v) << NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL_SHIFT)
#define NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL_INSERT(x, v) \
        ((x) | ((v) << NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL_SHIFT))
#define NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL_MASK) | ((v) << NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL_SHIFT))
#define NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL_EXTRACT(x) \
        (((x) & NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL_MASK) >> NDP120_DNN_CONFIG_DNNPARAMSSTS_RETN_CNTRL_SHIFT)

/*
 * block ndp120.pll_config, base 0x4000e000
 */
#define NDP120_PLL_CONFIG 0x4000e000U
#define NDP120_PLL_CONFIG_SIZE 0x00001000U
/* register ndp120.pll_config.pllctl0 */
#define NDP120_PLL_CONFIG_PLLCTL0 0x4000e000U
#define NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_SHIFT 2
#define NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_MASK 0x00000004U
#define NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_MASK) >> NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_CLKPLL_BYPASS_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_SHIFT 3
#define NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_MASK 0x00000008U
#define NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_MASK) >> NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_PLL_ENABLE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_SHIFT 4
#define NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_MASK 0x00000010U
#define NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_MASK) >> NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_LOCK_TIMEOUT_ENABLE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_SHIFT 5
#define NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_MASK 0x00000020U
#define NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_MASK) >> NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_CLKREF_SWITCH_ENABLE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_SHIFT 6
#define NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_MASK 0x00000040U
#define NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_MASK) >> NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_DLF_ENABLE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_SHIFT 7
#define NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_MASK 0x00000080U
#define NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_MASK) >> NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_DCO_NORM_ENABLE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_SHIFT 8
#define NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_MASK 0x00000100U
#define NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_MASK) >> NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_FREQ_ACQ_ENABLE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_SHIFT 11
#define NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_MASK 0x00000800U
#define NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_MASK) >> NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL0_OPEN_LOOP_BYPASS_ENABLE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL0_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl1 */
#define NDP120_PLL_CONFIG_PLLCTL1 0x4000e004U
#define NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_MASK 0x0000000fU
#define NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_MASK) >> NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL1_FCW_PREFIV_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL1_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl2 */
#define NDP120_PLL_CONFIG_PLLCTL2 0x4000e008U
#define NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_MASK 0x00000fffU
#define NDP120_PLL_CONFIG_PLLCTL2_FCW_INT(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_MASK) >> NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL2_FCW_INT_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL2_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl3 */
#define NDP120_PLL_CONFIG_PLLCTL3 0x4000e00cU
#define NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_MASK 0x00000007U
#define NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_MASK) >> NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL3_FCW_FRAC_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL3_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl4 */
#define NDP120_PLL_CONFIG_PLLCTL4 0x4000e010U
#define NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_MASK 0x00003fffU
#define NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_MASK) >> NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL4_DLF_LOCKED_KP_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL4_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl5 */
#define NDP120_PLL_CONFIG_PLLCTL5 0x4000e014U
#define NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_MASK 0x00003fffU
#define NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_MASK) >> NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL5_DLF_LOCKED_KI_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL5_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl6 */
#define NDP120_PLL_CONFIG_PLLCTL6 0x4000e01cU
#define NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_MASK 0x00003fffU
#define NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_MASK) >> NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL6_DLF_TRACK_KP_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL6_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl7 */
#define NDP120_PLL_CONFIG_PLLCTL7 0x4000e020U
#define NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_MASK 0x00003fffU
#define NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_MASK) >> NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL7_DLF_TRACK_KI_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL7_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl8 */
#define NDP120_PLL_CONFIG_PLLCTL8 0x4000e028U
#define NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_MASK 0x000000ffU
#define NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_MASK) >> NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL8_LOCK_COUNT_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_SHIFT 8
#define NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_MASK 0x00000100U
#define NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_MASK) >> NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL8_FCW_LOL_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL8_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl9 */
#define NDP120_PLL_CONFIG_PLLCTL9 0x4000e02cU
#define NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_MASK 0x0000ffffU
#define NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_MASK) >> NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL9_LOCK_THRESHOLD_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL9_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl10 */
#define NDP120_PLL_CONFIG_PLLCTL10 0x4000e030U
#define NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_MASK 0x00000fffU
#define NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_MASK) >> NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL10_DCO_GAIN_FREF_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL10_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl11 */
#define NDP120_PLL_CONFIG_PLLCTL11 0x4000e038U
#define NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_MASK 0x0000000fU
#define NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_MASK) >> NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL11_POSTDIV0_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL11_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl12 */
#define NDP120_PLL_CONFIG_PLLCTL12 0x4000e048U
#define NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_SHIFT 14
#define NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_MASK 0x01ffc000U
#define NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_MASK) >> NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL12_POSTDIV0_POWERDOWN_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL12_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl13 */
#define NDP120_PLL_CONFIG_PLLCTL13 0x4000e058U
#define NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_MASK 0x00000001U
#define NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_MASK) >> NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL13_POSTDIV0_BYPASS_ENABLE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL13_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl14 */
#define NDP120_PLL_CONFIG_PLLCTL14 0x4000e05cU
#define NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_MASK 0x000001ffU
#define NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_MASK) >> NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL14_OPEN_LOOP_CODE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL14_DEFAULT 0x00000000U 
/* register ndp120.pll_config.plltrim */
#define NDP120_PLL_CONFIG_PLLTRIM 0x4000e060U
#define NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_SHIFT 2
#define NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_MASK 0x0000003cU
#define NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM(v) \
        ((v) << NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_SHIFT)
#define NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_SHIFT))
#define NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_MASK) | ((v) << NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_SHIFT))
#define NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_MASK) >> NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_SHIFT)
#define NDP120_PLL_CONFIG_PLLTRIM_LDO_REF_TRIM_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLTRIM_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl15 */
#define NDP120_PLL_CONFIG_PLLCTL15 0x4000e064U
#define NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_MASK 0x00000001U
#define NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_MASK) >> NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL15_SAMPLE_STROBE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_SHIFT 1
#define NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_MASK 0x00000002U
#define NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_MASK) >> NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL15_LOCK_MONITOR_CLEAR_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL15_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl16 */
#define NDP120_PLL_CONFIG_PLLCTL16 0x4000e068U
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_MASK 0x00000001U
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_MASK) >> NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_AUTO_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_SHIFT 1
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_MASK 0x00000002U
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_MASK) >> NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL16_MUTE_FORCE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL16_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl17 */
#define NDP120_PLL_CONFIG_PLLCTL17 0x4000e080U
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_MASK 0x00000007U
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_MASK) >> NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_CAP_TRIM_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_SHIFT 3
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_MASK 0x00000008U
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_MASK) >> NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL17_OSC_POWER_MODE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL17_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl18 */
#define NDP120_PLL_CONFIG_PLLCTL18 0x4000e084U
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_MASK 0x00000001U
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_MASK) >> NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_SEL_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_SHIFT 4
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_MASK 0x00000010U
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_MASK) >> NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL18_PHASE_OBS_EN_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL18_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl19 */
#define NDP120_PLL_CONFIG_PLLCTL19 0x4000e08cU
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_MASK 0x00000001U
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_MASK) >> NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_ENABLE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_SHIFT 1
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_MASK 0x0000003eU
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_MASK) >> NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLKREF_DIV_CODE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_SHIFT 6
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_MASK 0x000007c0U
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_MASK) >> NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_DIV_CODE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_SHIFT 11
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_MASK 0x00007800U
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_MASK) >> NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL19_FREQ_MONITOR_CLK_SEL_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL19_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl20 */
#define NDP120_PLL_CONFIG_PLLCTL20 0x4000e090U
#define NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_MASK 0x0000ffffU
#define NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_MASK) >> NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL20_FREQ_MONITOR_CLKREF_COUNT_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL20_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl21 */
#define NDP120_PLL_CONFIG_PLLCTL21 0x4000e094U
#define NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_MASK 0x0000ffffU
#define NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_MASK) >> NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL21_FREQ_MONITOR_CLK_COUNT0_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL21_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl22 */
#define NDP120_PLL_CONFIG_PLLCTL22 0x4000e098U
#define NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_MASK 0x0000ffffU
#define NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_MASK) >> NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL22_FREQ_MONITOR_CLK_COUNT1_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL22_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllctl23 */
#define NDP120_PLL_CONFIG_PLLCTL23 0x4000e09cU
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_MASK 0x0000001fU
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_MASK) >> NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_ITER_LIMIT_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_SHIFT 5
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_MASK 0x000003e0U
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_MASK) >> NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL23_DCO_NORM_THRESHOLD_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL23_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllsts0 */
#define NDP120_PLL_CONFIG_PLLSTS0 0x4000e0c0U
#define NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR_SHIFT 0
#define NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR_MASK 0x0000ffffU
#define NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR(v) \
        ((v) << NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR_MASK) | ((v) << NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR_MASK) >> NDP120_PLL_CONFIG_PLLSTS0_LOCK_MONITOR_SHIFT)
/* register ndp120.pll_config.pllsts1 */
#define NDP120_PLL_CONFIG_PLLSTS1 0x4000e0c4U
#define NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED_SHIFT 0
#define NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED_MASK 0x0000ffffU
#define NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED(v) \
        ((v) << NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED_MASK) | ((v) << NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED_MASK) >> NDP120_PLL_CONFIG_PLLSTS1_DCO_CODE_ACQUIRED_SHIFT)
/* register ndp120.pll_config.pllsts2 */
#define NDP120_PLL_CONFIG_PLLSTS2 0x4000e0c8U
#define NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER_SHIFT 0
#define NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER_MASK 0x0000ffffU
#define NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER(v) \
        ((v) << NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER_MASK) | ((v) << NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER_MASK) >> NDP120_PLL_CONFIG_PLLSTS2_DCO_CODE_LOOP_FILTER_SHIFT)
/* register ndp120.pll_config.pllsts3 */
#define NDP120_PLL_CONFIG_PLLSTS3 0x4000e0ccU
#define NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM_SHIFT 0
#define NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM_MASK 0x0000ffffU
#define NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM(v) \
        ((v) << NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM_MASK) | ((v) << NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM_MASK) >> NDP120_PLL_CONFIG_PLLSTS3_DLF_SLOW_KI_NORM_SHIFT)
/* register ndp120.pll_config.pllsts4 */
#define NDP120_PLL_CONFIG_PLLSTS4 0x4000e0d0U
#define NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM_SHIFT 0
#define NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM_MASK 0x0000ffffU
#define NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM(v) \
        ((v) << NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM_MASK) | ((v) << NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM_MASK) >> NDP120_PLL_CONFIG_PLLSTS4_DLF_SLOW_KP_NORM_SHIFT)
/* register ndp120.pll_config.pllsts5 */
#define NDP120_PLL_CONFIG_PLLSTS5 0x4000e0d4U
#define NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM_SHIFT 0
#define NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM_MASK 0x0000ffffU
#define NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM(v) \
        ((v) << NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM_MASK) | ((v) << NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM_MASK) >> NDP120_PLL_CONFIG_PLLSTS5_DLF_FAST_KI_NORM_SHIFT)
/* register ndp120.pll_config.pllsts6 */
#define NDP120_PLL_CONFIG_PLLSTS6 0x4000e0d8U
#define NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM_SHIFT 0
#define NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM_MASK 0x0000ffffU
#define NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM(v) \
        ((v) << NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM_MASK) | ((v) << NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM_MASK) >> NDP120_PLL_CONFIG_PLLSTS6_DLF_FAST_KP_NORM_SHIFT)
/* register ndp120.pll_config.pllctl24 */
#define NDP120_PLL_CONFIG_PLLCTL24 0x4000e0e0U
#define NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_SHIFT 0
#define NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_MASK 0x00000001U
#define NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_SHIFT))
#define NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_MASK) >> NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_SHIFT)
#define NDP120_PLL_CONFIG_PLLCTL24_REG_UPDATE_DEFAULT 0x00000000U
#define NDP120_PLL_CONFIG_PLLCTL24_DEFAULT 0x00000000U 
/* register ndp120.pll_config.pllsts7 */
#define NDP120_PLL_CONFIG_PLLSTS7 0x4000e0e4U
#define NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT_SHIFT 0
#define NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT_MASK 0x00000001U
#define NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT(v) \
        ((v) << NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT_MASK) | ((v) << NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT_MASK) >> NDP120_PLL_CONFIG_PLLSTS7_LOCK_DETECT_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS7_MUTED_SHIFT 1
#define NDP120_PLL_CONFIG_PLLSTS7_MUTED_MASK 0x00000002U
#define NDP120_PLL_CONFIG_PLLSTS7_MUTED(v) \
        ((v) << NDP120_PLL_CONFIG_PLLSTS7_MUTED_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS7_MUTED_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLSTS7_MUTED_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS7_MUTED_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLSTS7_MUTED_MASK) | ((v) << NDP120_PLL_CONFIG_PLLSTS7_MUTED_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS7_MUTED_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLSTS7_MUTED_MASK) >> NDP120_PLL_CONFIG_PLLSTS7_MUTED_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE_SHIFT 8
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE_MASK 0x00000100U
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE(v) \
        ((v) << NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE_MASK) | ((v) << NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE_MASK) >> NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_DONE_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS_SHIFT 9
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS_MASK 0x00000200U
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS(v) \
        ((v) << NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS_SHIFT)
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS_INSERT(x, v) \
        ((x) | ((v) << NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS_MASK_INSERT(x, v) \
        (((x) & ~NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS_MASK) | ((v) << NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS_SHIFT))
#define NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS_EXTRACT(x) \
        (((x) & NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS_MASK) >> NDP120_PLL_CONFIG_PLLSTS7_FREQ_MONITOR_PASS_SHIFT)

/*
 * block ndp120.gpio1, base 0x40010000
 */
#define NDP120_GPIO1 0x40010000U
#define NDP120_GPIO1_SIZE 0x00001000U
/* register ndp120.gpio1.datain */
#define NDP120_GPIO1_DATAIN 0x40010000U
#define NDP120_GPIO1_DATAIN_VAL_SHIFT 0
#define NDP120_GPIO1_DATAIN_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_DATAIN_VAL(v) \
        ((v) << NDP120_GPIO1_DATAIN_VAL_SHIFT)
#define NDP120_GPIO1_DATAIN_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_DATAIN_VAL_SHIFT))
#define NDP120_GPIO1_DATAIN_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_DATAIN_VAL_MASK) | ((v) << NDP120_GPIO1_DATAIN_VAL_SHIFT))
#define NDP120_GPIO1_DATAIN_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_DATAIN_VAL_MASK) >> NDP120_GPIO1_DATAIN_VAL_SHIFT)
#define NDP120_GPIO1_DATAIN_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_DATAIN_DEFAULT 0x00000000U 
/* register ndp120.gpio1.dataout */
#define NDP120_GPIO1_DATAOUT 0x40010004U
#define NDP120_GPIO1_DATAOUT_VAL_SHIFT 0
#define NDP120_GPIO1_DATAOUT_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_DATAOUT_VAL(v) \
        ((v) << NDP120_GPIO1_DATAOUT_VAL_SHIFT)
#define NDP120_GPIO1_DATAOUT_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_DATAOUT_VAL_SHIFT))
#define NDP120_GPIO1_DATAOUT_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_DATAOUT_VAL_MASK) | ((v) << NDP120_GPIO1_DATAOUT_VAL_SHIFT))
#define NDP120_GPIO1_DATAOUT_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_DATAOUT_VAL_MASK) >> NDP120_GPIO1_DATAOUT_VAL_SHIFT)
#define NDP120_GPIO1_DATAOUT_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_DATAOUT_DEFAULT 0x00000000U 
/* register ndp120.gpio1.outset */
#define NDP120_GPIO1_OUTSET 0x40010010U
#define NDP120_GPIO1_OUTSET_VAL_SHIFT 0
#define NDP120_GPIO1_OUTSET_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_OUTSET_VAL(v) \
        ((v) << NDP120_GPIO1_OUTSET_VAL_SHIFT)
#define NDP120_GPIO1_OUTSET_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_OUTSET_VAL_SHIFT))
#define NDP120_GPIO1_OUTSET_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_OUTSET_VAL_MASK) | ((v) << NDP120_GPIO1_OUTSET_VAL_SHIFT))
#define NDP120_GPIO1_OUTSET_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_OUTSET_VAL_MASK) >> NDP120_GPIO1_OUTSET_VAL_SHIFT)
#define NDP120_GPIO1_OUTSET_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_OUTSET_DEFAULT 0x00000000U 
/* register ndp120.gpio1.outclr */
#define NDP120_GPIO1_OUTCLR 0x40010014U
#define NDP120_GPIO1_OUTCLR_VAL_SHIFT 0
#define NDP120_GPIO1_OUTCLR_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_OUTCLR_VAL(v) \
        ((v) << NDP120_GPIO1_OUTCLR_VAL_SHIFT)
#define NDP120_GPIO1_OUTCLR_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_OUTCLR_VAL_SHIFT))
#define NDP120_GPIO1_OUTCLR_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_OUTCLR_VAL_MASK) | ((v) << NDP120_GPIO1_OUTCLR_VAL_SHIFT))
#define NDP120_GPIO1_OUTCLR_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_OUTCLR_VAL_MASK) >> NDP120_GPIO1_OUTCLR_VAL_SHIFT)
#define NDP120_GPIO1_OUTCLR_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_OUTCLR_DEFAULT 0x00000000U 
/* register ndp120.gpio1.altset */
#define NDP120_GPIO1_ALTSET 0x40010018U
#define NDP120_GPIO1_ALTSET_VAL_SHIFT 0
#define NDP120_GPIO1_ALTSET_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_ALTSET_VAL(v) \
        ((v) << NDP120_GPIO1_ALTSET_VAL_SHIFT)
#define NDP120_GPIO1_ALTSET_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_ALTSET_VAL_SHIFT))
#define NDP120_GPIO1_ALTSET_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_ALTSET_VAL_MASK) | ((v) << NDP120_GPIO1_ALTSET_VAL_SHIFT))
#define NDP120_GPIO1_ALTSET_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_ALTSET_VAL_MASK) >> NDP120_GPIO1_ALTSET_VAL_SHIFT)
#define NDP120_GPIO1_ALTSET_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_ALTSET_DEFAULT 0x00000000U 
/* register ndp120.gpio1.altclr */
#define NDP120_GPIO1_ALTCLR 0x4001001cU
#define NDP120_GPIO1_ALTCLR_VAL_SHIFT 0
#define NDP120_GPIO1_ALTCLR_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_ALTCLR_VAL(v) \
        ((v) << NDP120_GPIO1_ALTCLR_VAL_SHIFT)
#define NDP120_GPIO1_ALTCLR_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_ALTCLR_VAL_SHIFT))
#define NDP120_GPIO1_ALTCLR_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_ALTCLR_VAL_MASK) | ((v) << NDP120_GPIO1_ALTCLR_VAL_SHIFT))
#define NDP120_GPIO1_ALTCLR_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_ALTCLR_VAL_MASK) >> NDP120_GPIO1_ALTCLR_VAL_SHIFT)
#define NDP120_GPIO1_ALTCLR_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_ALTCLR_DEFAULT 0x00000000U 
/* register ndp120.gpio1.intenset */
#define NDP120_GPIO1_INTENSET 0x40010020U
#define NDP120_GPIO1_INTENSET_VAL_SHIFT 0
#define NDP120_GPIO1_INTENSET_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_INTENSET_VAL(v) \
        ((v) << NDP120_GPIO1_INTENSET_VAL_SHIFT)
#define NDP120_GPIO1_INTENSET_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_INTENSET_VAL_SHIFT))
#define NDP120_GPIO1_INTENSET_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_INTENSET_VAL_MASK) | ((v) << NDP120_GPIO1_INTENSET_VAL_SHIFT))
#define NDP120_GPIO1_INTENSET_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_INTENSET_VAL_MASK) >> NDP120_GPIO1_INTENSET_VAL_SHIFT)
#define NDP120_GPIO1_INTENSET_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_INTENSET_DEFAULT 0x00000000U 
/* register ndp120.gpio1.intenclr */
#define NDP120_GPIO1_INTENCLR 0x40010024U
#define NDP120_GPIO1_INTENCLR_VAL_SHIFT 0
#define NDP120_GPIO1_INTENCLR_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_INTENCLR_VAL(v) \
        ((v) << NDP120_GPIO1_INTENCLR_VAL_SHIFT)
#define NDP120_GPIO1_INTENCLR_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_INTENCLR_VAL_SHIFT))
#define NDP120_GPIO1_INTENCLR_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_INTENCLR_VAL_MASK) | ((v) << NDP120_GPIO1_INTENCLR_VAL_SHIFT))
#define NDP120_GPIO1_INTENCLR_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_INTENCLR_VAL_MASK) >> NDP120_GPIO1_INTENCLR_VAL_SHIFT)
#define NDP120_GPIO1_INTENCLR_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_INTENCLR_DEFAULT 0x00000000U 
/* register ndp120.gpio1.inttypeset */
#define NDP120_GPIO1_INTTYPESET 0x40010028U
#define NDP120_GPIO1_INTTYPESET_VAL_SHIFT 0
#define NDP120_GPIO1_INTTYPESET_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_INTTYPESET_VAL(v) \
        ((v) << NDP120_GPIO1_INTTYPESET_VAL_SHIFT)
#define NDP120_GPIO1_INTTYPESET_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_INTTYPESET_VAL_SHIFT))
#define NDP120_GPIO1_INTTYPESET_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_INTTYPESET_VAL_MASK) | ((v) << NDP120_GPIO1_INTTYPESET_VAL_SHIFT))
#define NDP120_GPIO1_INTTYPESET_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_INTTYPESET_VAL_MASK) >> NDP120_GPIO1_INTTYPESET_VAL_SHIFT)
#define NDP120_GPIO1_INTTYPESET_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_INTTYPESET_DEFAULT 0x00000000U 
/* register ndp120.gpio1.inttypeclr */
#define NDP120_GPIO1_INTTYPECLR 0x4001002cU
#define NDP120_GPIO1_INTTYPECLR_VAL_SHIFT 0
#define NDP120_GPIO1_INTTYPECLR_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_INTTYPECLR_VAL(v) \
        ((v) << NDP120_GPIO1_INTTYPECLR_VAL_SHIFT)
#define NDP120_GPIO1_INTTYPECLR_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_INTTYPECLR_VAL_SHIFT))
#define NDP120_GPIO1_INTTYPECLR_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_INTTYPECLR_VAL_MASK) | ((v) << NDP120_GPIO1_INTTYPECLR_VAL_SHIFT))
#define NDP120_GPIO1_INTTYPECLR_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_INTTYPECLR_VAL_MASK) >> NDP120_GPIO1_INTTYPECLR_VAL_SHIFT)
#define NDP120_GPIO1_INTTYPECLR_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_INTTYPECLR_DEFAULT 0x00000000U 
/* register ndp120.gpio1.intpolset */
#define NDP120_GPIO1_INTPOLSET 0x40010030U
#define NDP120_GPIO1_INTPOLSET_VAL_SHIFT 0
#define NDP120_GPIO1_INTPOLSET_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_INTPOLSET_VAL(v) \
        ((v) << NDP120_GPIO1_INTPOLSET_VAL_SHIFT)
#define NDP120_GPIO1_INTPOLSET_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_INTPOLSET_VAL_SHIFT))
#define NDP120_GPIO1_INTPOLSET_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_INTPOLSET_VAL_MASK) | ((v) << NDP120_GPIO1_INTPOLSET_VAL_SHIFT))
#define NDP120_GPIO1_INTPOLSET_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_INTPOLSET_VAL_MASK) >> NDP120_GPIO1_INTPOLSET_VAL_SHIFT)
#define NDP120_GPIO1_INTPOLSET_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_INTPOLSET_DEFAULT 0x00000000U 
/* register ndp120.gpio1.intpolclr */
#define NDP120_GPIO1_INTPOLCLR 0x40010034U
#define NDP120_GPIO1_INTPOLCLR_VAL_SHIFT 0
#define NDP120_GPIO1_INTPOLCLR_VAL_MASK 0x0000ffffU
#define NDP120_GPIO1_INTPOLCLR_VAL(v) \
        ((v) << NDP120_GPIO1_INTPOLCLR_VAL_SHIFT)
#define NDP120_GPIO1_INTPOLCLR_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO1_INTPOLCLR_VAL_SHIFT))
#define NDP120_GPIO1_INTPOLCLR_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO1_INTPOLCLR_VAL_MASK) | ((v) << NDP120_GPIO1_INTPOLCLR_VAL_SHIFT))
#define NDP120_GPIO1_INTPOLCLR_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO1_INTPOLCLR_VAL_MASK) >> NDP120_GPIO1_INTPOLCLR_VAL_SHIFT)
#define NDP120_GPIO1_INTPOLCLR_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO1_INTPOLCLR_DEFAULT 0x00000000U 

/*
 * block ndp120.gpio, base 0x40011000
 */
#define NDP120_GPIO 0x40011000U
#define NDP120_GPIO_SIZE 0x00001000U
/* register ndp120.gpio.datain */
#define NDP120_GPIO_DATAIN 0x40011000U
#define NDP120_GPIO_DATAIN_VAL_SHIFT 0
#define NDP120_GPIO_DATAIN_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_DATAIN_VAL(v) \
        ((v) << NDP120_GPIO_DATAIN_VAL_SHIFT)
#define NDP120_GPIO_DATAIN_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_DATAIN_VAL_SHIFT))
#define NDP120_GPIO_DATAIN_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_DATAIN_VAL_MASK) | ((v) << NDP120_GPIO_DATAIN_VAL_SHIFT))
#define NDP120_GPIO_DATAIN_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_DATAIN_VAL_MASK) >> NDP120_GPIO_DATAIN_VAL_SHIFT)
#define NDP120_GPIO_DATAIN_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_DATAIN_DEFAULT 0x00000000U 
/* register ndp120.gpio.dataout */
#define NDP120_GPIO_DATAOUT 0x40011004U
#define NDP120_GPIO_DATAOUT_VAL_SHIFT 0
#define NDP120_GPIO_DATAOUT_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_DATAOUT_VAL(v) \
        ((v) << NDP120_GPIO_DATAOUT_VAL_SHIFT)
#define NDP120_GPIO_DATAOUT_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_DATAOUT_VAL_SHIFT))
#define NDP120_GPIO_DATAOUT_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_DATAOUT_VAL_MASK) | ((v) << NDP120_GPIO_DATAOUT_VAL_SHIFT))
#define NDP120_GPIO_DATAOUT_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_DATAOUT_VAL_MASK) >> NDP120_GPIO_DATAOUT_VAL_SHIFT)
#define NDP120_GPIO_DATAOUT_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_DATAOUT_DEFAULT 0x00000000U 
/* register ndp120.gpio.outset */
#define NDP120_GPIO_OUTSET 0x40011010U
#define NDP120_GPIO_OUTSET_VAL_SHIFT 0
#define NDP120_GPIO_OUTSET_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_OUTSET_VAL(v) \
        ((v) << NDP120_GPIO_OUTSET_VAL_SHIFT)
#define NDP120_GPIO_OUTSET_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_OUTSET_VAL_SHIFT))
#define NDP120_GPIO_OUTSET_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_OUTSET_VAL_MASK) | ((v) << NDP120_GPIO_OUTSET_VAL_SHIFT))
#define NDP120_GPIO_OUTSET_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_OUTSET_VAL_MASK) >> NDP120_GPIO_OUTSET_VAL_SHIFT)
#define NDP120_GPIO_OUTSET_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_OUTSET_DEFAULT 0x00000000U 
/* register ndp120.gpio.outclr */
#define NDP120_GPIO_OUTCLR 0x40011014U
#define NDP120_GPIO_OUTCLR_VAL_SHIFT 0
#define NDP120_GPIO_OUTCLR_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_OUTCLR_VAL(v) \
        ((v) << NDP120_GPIO_OUTCLR_VAL_SHIFT)
#define NDP120_GPIO_OUTCLR_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_OUTCLR_VAL_SHIFT))
#define NDP120_GPIO_OUTCLR_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_OUTCLR_VAL_MASK) | ((v) << NDP120_GPIO_OUTCLR_VAL_SHIFT))
#define NDP120_GPIO_OUTCLR_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_OUTCLR_VAL_MASK) >> NDP120_GPIO_OUTCLR_VAL_SHIFT)
#define NDP120_GPIO_OUTCLR_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_OUTCLR_DEFAULT 0x00000000U 
/* register ndp120.gpio.altset */
#define NDP120_GPIO_ALTSET 0x40011018U
#define NDP120_GPIO_ALTSET_VAL_SHIFT 0
#define NDP120_GPIO_ALTSET_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_ALTSET_VAL(v) \
        ((v) << NDP120_GPIO_ALTSET_VAL_SHIFT)
#define NDP120_GPIO_ALTSET_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_ALTSET_VAL_SHIFT))
#define NDP120_GPIO_ALTSET_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_ALTSET_VAL_MASK) | ((v) << NDP120_GPIO_ALTSET_VAL_SHIFT))
#define NDP120_GPIO_ALTSET_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_ALTSET_VAL_MASK) >> NDP120_GPIO_ALTSET_VAL_SHIFT)
#define NDP120_GPIO_ALTSET_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_ALTSET_DEFAULT 0x00000000U 
/* register ndp120.gpio.altclr */
#define NDP120_GPIO_ALTCLR 0x4001101cU
#define NDP120_GPIO_ALTCLR_VAL_SHIFT 0
#define NDP120_GPIO_ALTCLR_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_ALTCLR_VAL(v) \
        ((v) << NDP120_GPIO_ALTCLR_VAL_SHIFT)
#define NDP120_GPIO_ALTCLR_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_ALTCLR_VAL_SHIFT))
#define NDP120_GPIO_ALTCLR_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_ALTCLR_VAL_MASK) | ((v) << NDP120_GPIO_ALTCLR_VAL_SHIFT))
#define NDP120_GPIO_ALTCLR_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_ALTCLR_VAL_MASK) >> NDP120_GPIO_ALTCLR_VAL_SHIFT)
#define NDP120_GPIO_ALTCLR_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_ALTCLR_DEFAULT 0x00000000U 
/* register ndp120.gpio.intenset */
#define NDP120_GPIO_INTENSET 0x40011020U
#define NDP120_GPIO_INTENSET_VAL_SHIFT 0
#define NDP120_GPIO_INTENSET_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_INTENSET_VAL(v) \
        ((v) << NDP120_GPIO_INTENSET_VAL_SHIFT)
#define NDP120_GPIO_INTENSET_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_INTENSET_VAL_SHIFT))
#define NDP120_GPIO_INTENSET_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_INTENSET_VAL_MASK) | ((v) << NDP120_GPIO_INTENSET_VAL_SHIFT))
#define NDP120_GPIO_INTENSET_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_INTENSET_VAL_MASK) >> NDP120_GPIO_INTENSET_VAL_SHIFT)
#define NDP120_GPIO_INTENSET_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_INTENSET_DEFAULT 0x00000000U 
/* register ndp120.gpio.intenclr */
#define NDP120_GPIO_INTENCLR 0x40011024U
#define NDP120_GPIO_INTENCLR_VAL_SHIFT 0
#define NDP120_GPIO_INTENCLR_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_INTENCLR_VAL(v) \
        ((v) << NDP120_GPIO_INTENCLR_VAL_SHIFT)
#define NDP120_GPIO_INTENCLR_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_INTENCLR_VAL_SHIFT))
#define NDP120_GPIO_INTENCLR_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_INTENCLR_VAL_MASK) | ((v) << NDP120_GPIO_INTENCLR_VAL_SHIFT))
#define NDP120_GPIO_INTENCLR_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_INTENCLR_VAL_MASK) >> NDP120_GPIO_INTENCLR_VAL_SHIFT)
#define NDP120_GPIO_INTENCLR_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_INTENCLR_DEFAULT 0x00000000U 
/* register ndp120.gpio.inttypeset */
#define NDP120_GPIO_INTTYPESET 0x40011028U
#define NDP120_GPIO_INTTYPESET_VAL_SHIFT 0
#define NDP120_GPIO_INTTYPESET_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_INTTYPESET_VAL(v) \
        ((v) << NDP120_GPIO_INTTYPESET_VAL_SHIFT)
#define NDP120_GPIO_INTTYPESET_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_INTTYPESET_VAL_SHIFT))
#define NDP120_GPIO_INTTYPESET_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_INTTYPESET_VAL_MASK) | ((v) << NDP120_GPIO_INTTYPESET_VAL_SHIFT))
#define NDP120_GPIO_INTTYPESET_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_INTTYPESET_VAL_MASK) >> NDP120_GPIO_INTTYPESET_VAL_SHIFT)
#define NDP120_GPIO_INTTYPESET_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_INTTYPESET_DEFAULT 0x00000000U 
/* register ndp120.gpio.inttypeclr */
#define NDP120_GPIO_INTTYPECLR 0x4001102cU
#define NDP120_GPIO_INTTYPECLR_VAL_SHIFT 0
#define NDP120_GPIO_INTTYPECLR_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_INTTYPECLR_VAL(v) \
        ((v) << NDP120_GPIO_INTTYPECLR_VAL_SHIFT)
#define NDP120_GPIO_INTTYPECLR_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_INTTYPECLR_VAL_SHIFT))
#define NDP120_GPIO_INTTYPECLR_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_INTTYPECLR_VAL_MASK) | ((v) << NDP120_GPIO_INTTYPECLR_VAL_SHIFT))
#define NDP120_GPIO_INTTYPECLR_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_INTTYPECLR_VAL_MASK) >> NDP120_GPIO_INTTYPECLR_VAL_SHIFT)
#define NDP120_GPIO_INTTYPECLR_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_INTTYPECLR_DEFAULT 0x00000000U 
/* register ndp120.gpio.intpolset */
#define NDP120_GPIO_INTPOLSET 0x40011030U
#define NDP120_GPIO_INTPOLSET_VAL_SHIFT 0
#define NDP120_GPIO_INTPOLSET_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_INTPOLSET_VAL(v) \
        ((v) << NDP120_GPIO_INTPOLSET_VAL_SHIFT)
#define NDP120_GPIO_INTPOLSET_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_INTPOLSET_VAL_SHIFT))
#define NDP120_GPIO_INTPOLSET_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_INTPOLSET_VAL_MASK) | ((v) << NDP120_GPIO_INTPOLSET_VAL_SHIFT))
#define NDP120_GPIO_INTPOLSET_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_INTPOLSET_VAL_MASK) >> NDP120_GPIO_INTPOLSET_VAL_SHIFT)
#define NDP120_GPIO_INTPOLSET_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_INTPOLSET_DEFAULT 0x00000000U 
/* register ndp120.gpio.intpolclr */
#define NDP120_GPIO_INTPOLCLR 0x40011034U
#define NDP120_GPIO_INTPOLCLR_VAL_SHIFT 0
#define NDP120_GPIO_INTPOLCLR_VAL_MASK 0x0000ffffU
#define NDP120_GPIO_INTPOLCLR_VAL(v) \
        ((v) << NDP120_GPIO_INTPOLCLR_VAL_SHIFT)
#define NDP120_GPIO_INTPOLCLR_VAL_INSERT(x, v) \
        ((x) | ((v) << NDP120_GPIO_INTPOLCLR_VAL_SHIFT))
#define NDP120_GPIO_INTPOLCLR_VAL_MASK_INSERT(x, v) \
        (((x) & ~NDP120_GPIO_INTPOLCLR_VAL_MASK) | ((v) << NDP120_GPIO_INTPOLCLR_VAL_SHIFT))
#define NDP120_GPIO_INTPOLCLR_VAL_EXTRACT(x) \
        (((x) & NDP120_GPIO_INTPOLCLR_VAL_MASK) >> NDP120_GPIO_INTPOLCLR_VAL_SHIFT)
#define NDP120_GPIO_INTPOLCLR_VAL_DEFAULT 0x00000000U
#define NDP120_GPIO_INTPOLCLR_DEFAULT 0x00000000U 

/*
 * block ndp120.sysctl, base 0x4001f000
 */
#define NDP120_SYSCTL 0x4001f000U
#define NDP120_SYSCTL_SIZE 0x00001000U
/* register ndp120.sysctl.memctrl */
#define NDP120_SYSCTL_MEMCTRL 0x4001f000U
#define NDP120_SYSCTL_MEMCTRL_REMAP_SHIFT 0
#define NDP120_SYSCTL_MEMCTRL_REMAP_MASK 0x00000001U
#define NDP120_SYSCTL_MEMCTRL_REMAP(v) \
        ((v) << NDP120_SYSCTL_MEMCTRL_REMAP_SHIFT)
#define NDP120_SYSCTL_MEMCTRL_REMAP_INSERT(x, v) \
        ((x) | ((v) << NDP120_SYSCTL_MEMCTRL_REMAP_SHIFT))
#define NDP120_SYSCTL_MEMCTRL_REMAP_MASK_INSERT(x, v) \
        (((x) & ~NDP120_SYSCTL_MEMCTRL_REMAP_MASK) | ((v) << NDP120_SYSCTL_MEMCTRL_REMAP_SHIFT))
#define NDP120_SYSCTL_MEMCTRL_REMAP_EXTRACT(x) \
        (((x) & NDP120_SYSCTL_MEMCTRL_REMAP_MASK) >> NDP120_SYSCTL_MEMCTRL_REMAP_SHIFT)
#define NDP120_SYSCTL_MEMCTRL_REMAP_DEFAULT 0x00000001U
#define NDP120_SYSCTL_MEMCTRL_DEFAULT 0x00000001U 

/*
 * block ndp120.dnndata0_0, base 0x60000000
 */
#define NDP120_DNNDATA0_0 0x60000000U
#define NDP120_DNNDATA0_0_SIZE 0x00020000U

/*
 * block ndp120.dnndata0_1, base 0x60020000
 */
#define NDP120_DNNDATA0_1 0x60020000U
#define NDP120_DNNDATA0_1_SIZE 0x00010000U

/*
 * block ndp120.dnndata1_0, base 0x60040000
 */
#define NDP120_DNNDATA1_0 0x60040000U
#define NDP120_DNNDATA1_0_SIZE 0x00020000U

/*
 * block ndp120.dnndata1_1, base 0x60060000
 */
#define NDP120_DNNDATA1_1 0x60060000U
#define NDP120_DNNDATA1_1_SIZE 0x00010000U

/*
 * block ndp120.dnnparams, base 0x60080000
 */
#define NDP120_DNNPARAMS 0x60080000U
#define NDP120_DNNPARAMS_SIZE 0x00080000U

/*
 * block ndp120.dnnparams2, base 0x60100000
 */
#define NDP120_DNNPARAMS2 0x60100000U
#define NDP120_DNNPARAMS2_SIZE 0x00020000U

/*
 * block ndp120.sysrom, base 0xf0001000
 */
#define NDP120_SYSROM 0xf0001000U
#define NDP120_SYSROM_SIZE 0x00001000U

#endif
